/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __SPI_DW_H__ #define __SPI_DW_H__ #include <linux/bits.h> #include <linux/completion.h> #include <linux/debugfs.h> #include <linux/irqreturn.h> #include <linux/io.h> #include <linux/scatterlist.h> #include <linux/spi/spi-mem.h> #include <linux/bitfield.h> /* Synopsys DW SSI IP-core virtual IDs */ #define DW_PSSI_ID … #define DW_HSSI_ID … /* Synopsys DW SSI component versions (FourCC sequence) */ #define DW_HSSI_102A … /* DW SSI IP-core ID and version check helpers */ #define dw_spi_ip_is(_dws, _ip) … #define __dw_spi_ver_cmp(_dws, _ip, _ver, _op) … #define dw_spi_ver_is(_dws, _ip, _ver) … #define dw_spi_ver_is_ge(_dws, _ip, _ver) … /* DW SPI controller capabilities */ #define DW_SPI_CAP_CS_OVERRIDE … #define DW_SPI_CAP_DFS32 … /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */ #define DW_SPI_CTRLR0 … #define DW_SPI_CTRLR1 … #define DW_SPI_SSIENR … #define DW_SPI_MWCR … #define DW_SPI_SER … #define DW_SPI_BAUDR … #define DW_SPI_TXFTLR … #define DW_SPI_RXFTLR … #define DW_SPI_TXFLR … #define DW_SPI_RXFLR … #define DW_SPI_SR … #define DW_SPI_IMR … #define DW_SPI_ISR … #define DW_SPI_RISR … #define DW_SPI_TXOICR … #define DW_SPI_RXOICR … #define DW_SPI_RXUICR … #define DW_SPI_MSTICR … #define DW_SPI_ICR … #define DW_SPI_DMACR … #define DW_SPI_DMATDLR … #define DW_SPI_DMARDLR … #define DW_SPI_IDR … #define DW_SPI_VERSION … #define DW_SPI_DR … #define DW_SPI_RX_SAMPLE_DLY … #define DW_SPI_CS_OVERRIDE … /* Bit fields in CTRLR0 (DWC APB SSI) */ #define DW_PSSI_CTRLR0_DFS_MASK … #define DW_PSSI_CTRLR0_DFS32_MASK … #define DW_PSSI_CTRLR0_FRF_MASK … #define DW_SPI_CTRLR0_FRF_MOTO_SPI … #define DW_SPI_CTRLR0_FRF_TI_SSP … #define DW_SPI_CTRLR0_FRF_NS_MICROWIRE … #define DW_SPI_CTRLR0_FRF_RESV … #define DW_PSSI_CTRLR0_MODE_MASK … #define DW_PSSI_CTRLR0_SCPHA … #define DW_PSSI_CTRLR0_SCPOL … #define DW_PSSI_CTRLR0_TMOD_MASK … #define DW_SPI_CTRLR0_TMOD_TR … #define DW_SPI_CTRLR0_TMOD_TO … #define DW_SPI_CTRLR0_TMOD_RO … #define DW_SPI_CTRLR0_TMOD_EPROMREAD … #define DW_PSSI_CTRLR0_SLV_OE … #define DW_PSSI_CTRLR0_SRL … #define DW_PSSI_CTRLR0_CFS … /* Bit fields in CTRLR0 (DWC SSI with AHB interface) */ #define DW_HSSI_CTRLR0_DFS_MASK … #define DW_HSSI_CTRLR0_FRF_MASK … #define DW_HSSI_CTRLR0_SCPHA … #define DW_HSSI_CTRLR0_SCPOL … #define DW_HSSI_CTRLR0_TMOD_MASK … #define DW_HSSI_CTRLR0_SRL … #define DW_HSSI_CTRLR0_MST … /* Bit fields in CTRLR1 */ #define DW_SPI_NDF_MASK … /* Bit fields in SR, 7 bits */ #define DW_SPI_SR_MASK … #define DW_SPI_SR_BUSY … #define DW_SPI_SR_TF_NOT_FULL … #define DW_SPI_SR_TF_EMPT … #define DW_SPI_SR_RF_NOT_EMPT … #define DW_SPI_SR_RF_FULL … #define DW_SPI_SR_TX_ERR … #define DW_SPI_SR_DCOL … /* Bit fields in ISR, IMR, RISR, 7 bits */ #define DW_SPI_INT_MASK … #define DW_SPI_INT_TXEI … #define DW_SPI_INT_TXOI … #define DW_SPI_INT_RXUI … #define DW_SPI_INT_RXOI … #define DW_SPI_INT_RXFI … #define DW_SPI_INT_MSTI … /* Bit fields in DMACR */ #define DW_SPI_DMACR_RDMAE … #define DW_SPI_DMACR_TDMAE … /* Mem/DMA operations helpers */ #define DW_SPI_WAIT_RETRIES … #define DW_SPI_BUF_SIZE … #define DW_SPI_GET_BYTE(_val, _idx) … /* Slave spi_transfer/spi_mem_op related */ struct dw_spi_cfg { … }; struct dw_spi; struct dw_spi_dma_ops { … }; struct dw_spi { … }; static inline u32 dw_readl(struct dw_spi *dws, u32 offset) { … } static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) { … } static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) { … } static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) { … } static inline void dw_spi_enable_chip(struct dw_spi *dws, int enable) { … } static inline void dw_spi_set_clk(struct dw_spi *dws, u16 div) { … } /* Disable IRQ bits */ static inline void dw_spi_mask_intr(struct dw_spi *dws, u32 mask) { … } /* Enable IRQ bits */ static inline void dw_spi_umask_intr(struct dw_spi *dws, u32 mask) { … } /* * This disables the SPI controller, interrupts, clears the interrupts status * and CS, then re-enables the controller back. Transmit and receive FIFO * buffers are cleared when the device is disabled. */ static inline void dw_spi_reset_chip(struct dw_spi *dws) { … } static inline void dw_spi_shutdown_chip(struct dw_spi *dws) { … } extern void dw_spi_set_cs(struct spi_device *spi, bool enable); extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, struct dw_spi_cfg *cfg); extern int dw_spi_check_status(struct dw_spi *dws, bool raw); extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws); extern void dw_spi_remove_host(struct dw_spi *dws); extern int dw_spi_suspend_host(struct dw_spi *dws); extern int dw_spi_resume_host(struct dw_spi *dws); #ifdef CONFIG_SPI_DW_DMA extern void dw_spi_dma_setup_mfld(struct dw_spi *dws); extern void dw_spi_dma_setup_generic(struct dw_spi *dws); #else static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {} static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {} #endif /* !CONFIG_SPI_DW_DMA */ #endif /* __SPI_DW_H__ */
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