// SPDX-License-Identifier: GPL-2.0-only /* * Designware SPI core controller driver (refer pxa2xx_spi.c) * * Copyright (c) 2009, Intel Corporation. */ #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/dma-mapping.h> #include <linux/interrupt.h> #include <linux/module.h> #include <linux/preempt.h> #include <linux/highmem.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> #include <linux/string.h> #include <linux/of.h> #include "internals.h" #include "spi-dw.h" #ifdef CONFIG_DEBUG_FS #include <linux/debugfs.h> #endif /* Slave spi_device related */ struct dw_spi_chip_data { … }; #ifdef CONFIG_DEBUG_FS #define DW_SPI_DBGFS_REG(_name, _off) … static const struct debugfs_reg32 dw_spi_dbgfs_regs[] = …; static void dw_spi_debugfs_init(struct dw_spi *dws) { … } static void dw_spi_debugfs_remove(struct dw_spi *dws) { … } #else static inline void dw_spi_debugfs_init(struct dw_spi *dws) { } static inline void dw_spi_debugfs_remove(struct dw_spi *dws) { } #endif /* CONFIG_DEBUG_FS */ void dw_spi_set_cs(struct spi_device *spi, bool enable) { … } EXPORT_SYMBOL_NS_GPL(…); /* Return the max entries we can fill into tx fifo */ static inline u32 dw_spi_tx_max(struct dw_spi *dws) { … } /* Return the max entries we should read out of rx fifo */ static inline u32 dw_spi_rx_max(struct dw_spi *dws) { … } static void dw_writer(struct dw_spi *dws) { … } static void dw_reader(struct dw_spi *dws) { … } int dw_spi_check_status(struct dw_spi *dws, bool raw) { … } EXPORT_SYMBOL_NS_GPL(…); static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws) { … } static irqreturn_t dw_spi_irq(int irq, void *dev_id) { … } static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi) { … } void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, struct dw_spi_cfg *cfg) { … } EXPORT_SYMBOL_NS_GPL(…); static void dw_spi_irq_setup(struct dw_spi *dws) { … } /* * The iterative procedure of the poll-based transfer is simple: write as much * as possible to the Tx FIFO, wait until the pending to receive data is ready * to be read, read it from the Rx FIFO and check whether the performed * procedure has been successful. * * Note this method the same way as the IRQ-based transfer won't work well for * the SPI devices connected to the controller with native CS due to the * automatic CS assertion/de-assertion. */ static int dw_spi_poll_transfer(struct dw_spi *dws, struct spi_transfer *transfer) { … } static int dw_spi_transfer_one(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *transfer) { … } static void dw_spi_handle_err(struct spi_controller *host, struct spi_message *msg) { … } static int dw_spi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op) { … } static bool dw_spi_supports_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static int dw_spi_init_mem_buf(struct dw_spi *dws, const struct spi_mem_op *op) { … } static void dw_spi_free_mem_buf(struct dw_spi *dws) { … } static int dw_spi_write_then_read(struct dw_spi *dws, struct spi_device *spi) { … } static inline bool dw_spi_ctlr_busy(struct dw_spi *dws) { … } static int dw_spi_wait_mem_op_done(struct dw_spi *dws) { … } static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi) { … } /* * The SPI memory operation implementation below is the best choice for the * devices, which are selected by the native chip-select lane. It's * specifically developed to workaround the problem with automatic chip-select * lane toggle when there is no data in the Tx FIFO buffer. Luckily the current * SPI-mem core calls exec_op() callback only if the GPIO-based CS is * unavailable. */ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } /* * Initialize the default memory operations if a glue layer hasn't specified * custom ones. Direct mapping operations will be preserved anyway since DW SPI * controller doesn't have an embedded dirmap interface. Note the memory * operations implemented in this driver is the best choice only for the DW APB * SSI controller with standard native CS functionality. If a hardware vendor * has fixed the automatic CS assertion/de-assertion peculiarity, then it will * be safer to use the normal SPI-messages-based transfers implementation. */ static void dw_spi_init_mem_ops(struct dw_spi *dws) { … } /* This may be called twice for each spi dev */ static int dw_spi_setup(struct spi_device *spi) { … } static void dw_spi_cleanup(struct spi_device *spi) { … } /* Restart the controller, disable all interrupts, clean rx fifo */ static void dw_spi_hw_init(struct device *dev, struct dw_spi *dws) { … } int dw_spi_add_host(struct device *dev, struct dw_spi *dws) { … } EXPORT_SYMBOL_NS_GPL(…); void dw_spi_remove_host(struct dw_spi *dws) { … } EXPORT_SYMBOL_NS_GPL(…); int dw_spi_suspend_host(struct dw_spi *dws) { … } EXPORT_SYMBOL_NS_GPL(…); int dw_spi_resume_host(struct dw_spi *dws) { … } EXPORT_SYMBOL_NS_GPL(…); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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