linux/drivers/spi/spi-dw-dma.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Special handling for DW DMA core
 *
 * Copyright (c) 2009, 2014 Intel Corporation.
 */

#include <linux/completion.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/irqreturn.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_data/dma-dw.h>
#include <linux/spi/spi.h>
#include <linux/types.h>

#include "spi-dw.h"

#define DW_SPI_RX_BUSY …
#define DW_SPI_RX_BURST_LEVEL …
#define DW_SPI_TX_BUSY …
#define DW_SPI_TX_BURST_LEVEL …

static bool dw_spi_dma_chan_filter(struct dma_chan *chan, void *param)
{ … }

static void dw_spi_dma_maxburst_init(struct dw_spi *dws)
{ … }

static int dw_spi_dma_caps_init(struct dw_spi *dws)
{ … }

static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
{ … }

static int dw_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
{ … }

static void dw_spi_dma_exit(struct dw_spi *dws)
{ … }

static irqreturn_t dw_spi_dma_transfer_handler(struct dw_spi *dws)
{ … }

static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes)
{ … }

static bool dw_spi_can_dma(struct spi_controller *host,
			   struct spi_device *spi, struct spi_transfer *xfer)
{ … }

static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed)
{ … }

static inline bool dw_spi_dma_tx_busy(struct dw_spi *dws)
{ … }

static int dw_spi_dma_wait_tx_done(struct dw_spi *dws,
				   struct spi_transfer *xfer)
{ … }

/*
 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
 * channel will clear a corresponding bit.
 */
static void dw_spi_dma_tx_done(void *arg)
{ … }

static int dw_spi_dma_config_tx(struct dw_spi *dws)
{ … }

static int dw_spi_dma_submit_tx(struct dw_spi *dws, struct scatterlist *sgl,
				unsigned int nents)
{ … }

static inline bool dw_spi_dma_rx_busy(struct dw_spi *dws)
{ … }

static int dw_spi_dma_wait_rx_done(struct dw_spi *dws)
{ … }

/*
 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
 * channel will clear a corresponding bit.
 */
static void dw_spi_dma_rx_done(void *arg)
{ … }

static int dw_spi_dma_config_rx(struct dw_spi *dws)
{ … }

static int dw_spi_dma_submit_rx(struct dw_spi *dws, struct scatterlist *sgl,
				unsigned int nents)
{ … }

static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
{ … }

static int dw_spi_dma_transfer_all(struct dw_spi *dws,
				   struct spi_transfer *xfer)
{ … }

/*
 * In case if at least one of the requested DMA channels doesn't support the
 * hardware accelerated SG list entries traverse, the DMA driver will most
 * likely work that around by performing the IRQ-based SG list entries
 * resubmission. That might and will cause a problem if the DMA Tx channel is
 * recharged and re-executed before the Rx DMA channel. Due to
 * non-deterministic IRQ-handler execution latency the DMA Tx channel will
 * start pushing data to the SPI bus before the Rx DMA channel is even
 * reinitialized with the next inbound SG list entry. By doing so the DMA Tx
 * channel will implicitly start filling the DW APB SSI Rx FIFO up, which while
 * the DMA Rx channel being recharged and re-executed will eventually be
 * overflown.
 *
 * In order to solve the problem we have to feed the DMA engine with SG list
 * entries one-by-one. It shall keep the DW APB SSI Tx and Rx FIFOs
 * synchronized and prevent the Rx FIFO overflow. Since in general the tx_sg
 * and rx_sg lists may have different number of entries of different lengths
 * (though total length should match) let's virtually split the SG-lists to the
 * set of DMA transfers, which length is a minimum of the ordered SG-entries
 * lengths. An ASCII-sketch of the implemented algo is following:
 *                  xfer->len
 *                |___________|
 * tx_sg list:    |___|____|__|
 * rx_sg list:    |_|____|____|
 * DMA transfers: |_|_|__|_|__|
 *
 * Note in order to have this workaround solving the denoted problem the DMA
 * engine driver should properly initialize the max_sg_burst capability and set
 * the DMA device max segment size parameter with maximum data block size the
 * DMA engine supports.
 */

static int dw_spi_dma_transfer_one(struct dw_spi *dws,
				   struct spi_transfer *xfer)
{ … }

static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
{ … }

static void dw_spi_dma_stop(struct dw_spi *dws)
{ … }

static const struct dw_spi_dma_ops dw_spi_dma_mfld_ops = …;

void dw_spi_dma_setup_mfld(struct dw_spi *dws)
{ … }
EXPORT_SYMBOL_NS_GPL(…);

static const struct dw_spi_dma_ops dw_spi_dma_generic_ops = …;

void dw_spi_dma_setup_generic(struct dw_spi *dws)
{ … }
EXPORT_SYMBOL_NS_GPL(…);