linux/drivers/spi/spi-cadence-quadspi.c

// SPDX-License-Identifier: GPL-2.0-only
//
// Driver for Cadence QSPI Controller
//
// Copyright Altera Corporation (C) 2012-2014. All rights reserved.
// Copyright Intel Corporation (C) 2019-2020. All rights reserved.
// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/firmware/xlnx-zynqmp.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/log2.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/sched.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>
#include <linux/timer.h>

#define CQSPI_NAME
#define CQSPI_MAX_CHIPSELECT

static_assert();

/* Quirks */
#define CQSPI_NEEDS_WR_DELAY
#define CQSPI_DISABLE_DAC_MODE
#define CQSPI_SUPPORT_EXTERNAL_DMA
#define CQSPI_NO_SUPPORT_WR_COMPLETION
#define CQSPI_SLOW_SRAM
#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR
#define CQSPI_RD_NO_IRQ

/* Capabilities */
#define CQSPI_SUPPORTS_OCTAL

#define CQSPI_OP_WIDTH(part)

enum {};

struct cqspi_st;

struct cqspi_flash_pdata {};

struct cqspi_st {};

struct cqspi_driver_platdata {};

/* Operation timeout value */
#define CQSPI_TIMEOUT_MS
#define CQSPI_READ_TIMEOUT_MS
#define CQSPI_BUSYWAIT_TIMEOUT_US

/* Runtime_pm autosuspend delay */
#define CQSPI_AUTOSUSPEND_TIMEOUT

#define CQSPI_DUMMY_CLKS_PER_BYTE
#define CQSPI_DUMMY_BYTES_MAX
#define CQSPI_DUMMY_CLKS_MAX

#define CQSPI_STIG_DATA_LEN_MAX

/* Register map */
#define CQSPI_REG_CONFIG
#define CQSPI_REG_CONFIG_ENABLE_MASK
#define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL
#define CQSPI_REG_CONFIG_DECODE_MASK
#define CQSPI_REG_CONFIG_CHIPSELECT_LSB
#define CQSPI_REG_CONFIG_DMA_MASK
#define CQSPI_REG_CONFIG_BAUD_LSB
#define CQSPI_REG_CONFIG_DTR_PROTO
#define CQSPI_REG_CONFIG_DUAL_OPCODE
#define CQSPI_REG_CONFIG_IDLE_LSB
#define CQSPI_REG_CONFIG_CHIPSELECT_MASK
#define CQSPI_REG_CONFIG_BAUD_MASK

#define CQSPI_REG_RD_INSTR
#define CQSPI_REG_RD_INSTR_OPCODE_LSB
#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB
#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB
#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB
#define CQSPI_REG_RD_INSTR_MODE_EN_LSB
#define CQSPI_REG_RD_INSTR_DUMMY_LSB
#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK
#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK
#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK
#define CQSPI_REG_RD_INSTR_DUMMY_MASK

#define CQSPI_REG_WR_INSTR
#define CQSPI_REG_WR_INSTR_OPCODE_LSB
#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB
#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB

#define CQSPI_REG_DELAY
#define CQSPI_REG_DELAY_TSLCH_LSB
#define CQSPI_REG_DELAY_TCHSH_LSB
#define CQSPI_REG_DELAY_TSD2D_LSB
#define CQSPI_REG_DELAY_TSHSL_LSB
#define CQSPI_REG_DELAY_TSLCH_MASK
#define CQSPI_REG_DELAY_TCHSH_MASK
#define CQSPI_REG_DELAY_TSD2D_MASK
#define CQSPI_REG_DELAY_TSHSL_MASK

#define CQSPI_REG_READCAPTURE
#define CQSPI_REG_READCAPTURE_BYPASS_LSB
#define CQSPI_REG_READCAPTURE_DELAY_LSB
#define CQSPI_REG_READCAPTURE_DELAY_MASK

#define CQSPI_REG_SIZE
#define CQSPI_REG_SIZE_ADDRESS_LSB
#define CQSPI_REG_SIZE_PAGE_LSB
#define CQSPI_REG_SIZE_BLOCK_LSB
#define CQSPI_REG_SIZE_ADDRESS_MASK
#define CQSPI_REG_SIZE_PAGE_MASK
#define CQSPI_REG_SIZE_BLOCK_MASK

#define CQSPI_REG_SRAMPARTITION
#define CQSPI_REG_INDIRECTTRIGGER

#define CQSPI_REG_DMA
#define CQSPI_REG_DMA_SINGLE_LSB
#define CQSPI_REG_DMA_BURST_LSB
#define CQSPI_REG_DMA_SINGLE_MASK
#define CQSPI_REG_DMA_BURST_MASK

#define CQSPI_REG_REMAP
#define CQSPI_REG_MODE_BIT

#define CQSPI_REG_SDRAMLEVEL
#define CQSPI_REG_SDRAMLEVEL_RD_LSB
#define CQSPI_REG_SDRAMLEVEL_WR_LSB
#define CQSPI_REG_SDRAMLEVEL_RD_MASK
#define CQSPI_REG_SDRAMLEVEL_WR_MASK

#define CQSPI_REG_WR_COMPLETION_CTRL
#define CQSPI_REG_WR_DISABLE_AUTO_POLL

#define CQSPI_REG_IRQSTATUS
#define CQSPI_REG_IRQMASK

#define CQSPI_REG_INDIRECTRD
#define CQSPI_REG_INDIRECTRD_START_MASK
#define CQSPI_REG_INDIRECTRD_CANCEL_MASK
#define CQSPI_REG_INDIRECTRD_DONE_MASK

#define CQSPI_REG_INDIRECTRDWATERMARK
#define CQSPI_REG_INDIRECTRDSTARTADDR
#define CQSPI_REG_INDIRECTRDBYTES

#define CQSPI_REG_CMDCTRL
#define CQSPI_REG_CMDCTRL_EXECUTE_MASK
#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK
#define CQSPI_REG_CMDCTRL_DUMMY_LSB
#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB
#define CQSPI_REG_CMDCTRL_WR_EN_LSB
#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB
#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB
#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB
#define CQSPI_REG_CMDCTRL_RD_EN_LSB
#define CQSPI_REG_CMDCTRL_OPCODE_LSB
#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK
#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK
#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK
#define CQSPI_REG_CMDCTRL_DUMMY_MASK

#define CQSPI_REG_INDIRECTWR
#define CQSPI_REG_INDIRECTWR_START_MASK
#define CQSPI_REG_INDIRECTWR_CANCEL_MASK
#define CQSPI_REG_INDIRECTWR_DONE_MASK

#define CQSPI_REG_INDIRECTWRWATERMARK
#define CQSPI_REG_INDIRECTWRSTARTADDR
#define CQSPI_REG_INDIRECTWRBYTES

#define CQSPI_REG_INDTRIG_ADDRRANGE

#define CQSPI_REG_CMDADDRESS
#define CQSPI_REG_CMDREADDATALOWER
#define CQSPI_REG_CMDREADDATAUPPER
#define CQSPI_REG_CMDWRITEDATALOWER
#define CQSPI_REG_CMDWRITEDATAUPPER

#define CQSPI_REG_POLLING_STATUS
#define CQSPI_REG_POLLING_STATUS_DUMMY_LSB

#define CQSPI_REG_OP_EXT_LOWER
#define CQSPI_REG_OP_EXT_READ_LSB
#define CQSPI_REG_OP_EXT_WRITE_LSB
#define CQSPI_REG_OP_EXT_STIG_LSB

#define CQSPI_REG_VERSAL_DMA_SRC_ADDR

#define CQSPI_REG_VERSAL_DMA_DST_ADDR
#define CQSPI_REG_VERSAL_DMA_DST_SIZE

#define CQSPI_REG_VERSAL_DMA_DST_CTRL

#define CQSPI_REG_VERSAL_DMA_DST_I_STS
#define CQSPI_REG_VERSAL_DMA_DST_I_EN
#define CQSPI_REG_VERSAL_DMA_DST_I_DIS
#define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK

#define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB

#define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL
#define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL

/* Interrupt status bits */
#define CQSPI_REG_IRQ_MODE_ERR
#define CQSPI_REG_IRQ_UNDERFLOW
#define CQSPI_REG_IRQ_IND_COMP
#define CQSPI_REG_IRQ_IND_RD_REJECT
#define CQSPI_REG_IRQ_WR_PROTECTED_ERR
#define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR
#define CQSPI_REG_IRQ_WATERMARK
#define CQSPI_REG_IRQ_IND_SRAM_FULL

#define CQSPI_IRQ_MASK_RD

#define CQSPI_IRQ_MASK_WR

#define CQSPI_IRQ_STATUS_MASK
#define CQSPI_DMA_UNALIGN

#define CQSPI_REG_VERSAL_DMA_VAL

static int cqspi_wait_for_bit(const struct cqspi_driver_platdata *ddata,
			      void __iomem *reg, const u32 mask, bool clr,
			      bool busywait)
{}

static bool cqspi_is_idle(struct cqspi_st *cqspi)
{}

static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
{}

static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi)
{}

static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
{}

static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op)
{}

static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op)
{}

static int cqspi_wait_idle(struct cqspi_st *cqspi)
{}

static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
{}

static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata,
				  const struct spi_mem_op *op,
				  unsigned int shift)
{}

static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
			    const struct spi_mem_op *op, unsigned int shift)
{}

static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
			      const struct spi_mem_op *op)
{}

static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
			       const struct spi_mem_op *op)
{}

static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
			    const struct spi_mem_op *op)
{}

static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
				       u8 *rxbuf, loff_t from_addr,
				       const size_t n_rx)
{}

static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
{}

static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata,
					  u_char *rxbuf, loff_t from_addr,
					  size_t n_rx)
{}

static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
			     const struct spi_mem_op *op)
{}

static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
					loff_t to_addr, const u8 *txbuf,
					const size_t n_tx)
{}

static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
{}

static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
					   const unsigned int ns_val)
{}

static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)
{}

static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
{}

static void cqspi_readdata_capture(struct cqspi_st *cqspi,
				   const bool bypass,
				   const unsigned int delay)
{}

static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
			    unsigned long sclk)
{}

static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
			   const struct spi_mem_op *op)
{}

static void cqspi_rx_dma_callback(void *param)
{}

static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
				     u_char *buf, loff_t from, size_t len)
{}

static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
			  const struct spi_mem_op *op)
{}

static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
{}

static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
{}

static bool cqspi_supports_mem_op(struct spi_mem *mem,
				  const struct spi_mem_op *op)
{}

static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
				    struct cqspi_flash_pdata *f_pdata,
				    struct device_node *np)
{}

static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
{}

static void cqspi_controller_init(struct cqspi_st *cqspi)
{}

static void cqspi_controller_detect_fifo_depth(struct cqspi_st *cqspi)
{}

static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
{}

static const char *cqspi_get_name(struct spi_mem *mem)
{}

static const struct spi_controller_mem_ops cqspi_mem_ops =;

static const struct spi_controller_mem_caps cqspi_mem_caps =;

static int cqspi_setup_flash(struct cqspi_st *cqspi)
{}

static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqspi_st *cqspi)
{}

static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct cqspi_st *cqspi)
{}
static int cqspi_probe(struct platform_device *pdev)
{}

static void cqspi_remove(struct platform_device *pdev)
{}

static int cqspi_runtime_suspend(struct device *dev)
{}

static int cqspi_runtime_resume(struct device *dev)
{}

static int cqspi_suspend(struct device *dev)
{}

static int cqspi_resume(struct device *dev)
{}

static const struct dev_pm_ops cqspi_dev_pm_ops =;

static const struct cqspi_driver_platdata cdns_qspi =;

static const struct cqspi_driver_platdata k2g_qspi =;

static const struct cqspi_driver_platdata am654_ospi =;

static const struct cqspi_driver_platdata intel_lgm_qspi =;

static const struct cqspi_driver_platdata socfpga_qspi =;

static const struct cqspi_driver_platdata versal_ospi =;

static const struct cqspi_driver_platdata jh7110_qspi =;

static const struct cqspi_driver_platdata pensando_cdns_qspi =;

static const struct cqspi_driver_platdata mobileye_eyeq5_ospi =;

static const struct of_device_id cqspi_dt_ids[] =;

MODULE_DEVICE_TABLE(of, cqspi_dt_ids);

static struct platform_driver cqspi_platform_driver =;

module_platform_driver();

MODULE_DESCRIPTION();
MODULE_LICENSE();
MODULE_ALIAS();
MODULE_AUTHOR();
MODULE_AUTHOR();
MODULE_AUTHOR();
MODULE_AUTHOR();
MODULE_AUTHOR();