// SPDX-License-Identifier: GPL-2.0-only /* * Memory-mapped interface driver for DW SPI Core * * Copyright (c) 2010, Octasic semiconductor. */ #include <linux/clk.h> #include <linux/err.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/slab.h> #include <linux/spi/spi.h> #include <linux/scatterlist.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/acpi.h> #include <linux/property.h> #include <linux/regmap.h> #include <linux/reset.h> #include "spi-dw.h" #define DRIVER_NAME … struct dw_spi_mmio { … }; #define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL … #define OCELOT_IF_SI_OWNER_OFFSET … #define JAGUAR2_IF_SI_OWNER_OFFSET … #define MSCC_IF_SI_OWNER_MASK … #define MSCC_IF_SI_OWNER_SISL … #define MSCC_IF_SI_OWNER_SIBM … #define MSCC_IF_SI_OWNER_SIMC … #define MSCC_SPI_MST_SW_MODE … #define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE … #define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) … #define SPARX5_FORCE_ENA … #define SPARX5_FORCE_VAL … struct dw_spi_mscc { … }; /* * Elba SoC does not use ssi, pin override is used for cs 0,1 and * gpios for cs 2,3 as defined in the device tree. * * cs: | 1 0 * bit: |---3-------2-------1-------0 * | cs1 cs1_ovr cs0 cs0_ovr */ #define ELBA_SPICS_REG … #define ELBA_SPICS_OFFSET(cs) … #define ELBA_SPICS_MASK(cs) … #define ELBA_SPICS_SET(cs, val) … /* * The Designware SPI controller (referred to as master in the documentation) * automatically deasserts chip select when the tx fifo is empty. The chip * selects then needs to be either driven as GPIOs or, for the first 4 using * the SPI boot controller registers. the final chip select is an OR gate * between the Designware SPI controller and the SPI boot controller. */ static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable) { … } static int dw_spi_mscc_init(struct platform_device *pdev, struct dw_spi_mmio *dwsmmio, const char *cpu_syscon, u32 if_si_owner_offset) { … } static int dw_spi_mscc_ocelot_init(struct platform_device *pdev, struct dw_spi_mmio *dwsmmio) { … } static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev, struct dw_spi_mmio *dwsmmio) { … } /* * The Designware SPI controller (referred to as master in the * documentation) automatically deasserts chip select when the tx fifo * is empty. The chip selects then needs to be driven by a CS override * register. enable is an active low signal. */ static void dw_spi_sparx5_set_cs(struct spi_device *spi, bool enable) { … } static int dw_spi_mscc_sparx5_init(struct platform_device *pdev, struct dw_spi_mmio *dwsmmio) { … } static int dw_spi_alpine_init(struct platform_device *pdev, struct dw_spi_mmio *dwsmmio) { … } static int dw_spi_pssi_init(struct platform_device *pdev, struct dw_spi_mmio *dwsmmio) { … } static int dw_spi_hssi_init(struct platform_device *pdev, struct dw_spi_mmio *dwsmmio) { … } static int dw_spi_intel_init(struct platform_device *pdev, struct dw_spi_mmio *dwsmmio) { … } /* * DMA-based mem ops are not configured for this device and are not tested. */ static int dw_spi_mountevans_imc_init(struct platform_device *pdev, struct dw_spi_mmio *dwsmmio) { … } static int dw_spi_canaan_k210_init(struct platform_device *pdev, struct dw_spi_mmio *dwsmmio) { … } static void dw_spi_elba_override_cs(struct regmap *syscon, int cs, int enable) { … } static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable) { … } static int dw_spi_elba_init(struct platform_device *pdev, struct dw_spi_mmio *dwsmmio) { … } static int dw_spi_mmio_probe(struct platform_device *pdev) { … } static void dw_spi_mmio_remove(struct platform_device *pdev) { … } static const struct of_device_id dw_spi_mmio_of_match[] = …; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); #ifdef CONFIG_ACPI static const struct acpi_device_id dw_spi_mmio_acpi_match[] = …; MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match); #endif static struct platform_driver dw_spi_mmio_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_IMPORT_NS(…);
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