// SPDX-License-Identifier: GPL-2.0-only /* * Driver for the Diolan DLN-2 USB-SPI adapter * * Copyright (c) 2014 Intel Corporation */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/mfd/dln2.h> #include <linux/spi/spi.h> #include <linux/pm_runtime.h> #include <asm/unaligned.h> #define DLN2_SPI_MODULE_ID … #define DLN2_SPI_CMD(cmd) … /* SPI commands */ #define DLN2_SPI_GET_PORT_COUNT … #define DLN2_SPI_ENABLE … #define DLN2_SPI_DISABLE … #define DLN2_SPI_IS_ENABLED … #define DLN2_SPI_SET_MODE … #define DLN2_SPI_GET_MODE … #define DLN2_SPI_SET_FRAME_SIZE … #define DLN2_SPI_GET_FRAME_SIZE … #define DLN2_SPI_SET_FREQUENCY … #define DLN2_SPI_GET_FREQUENCY … #define DLN2_SPI_READ_WRITE … #define DLN2_SPI_READ … #define DLN2_SPI_WRITE … #define DLN2_SPI_SET_DELAY_BETWEEN_SS … #define DLN2_SPI_GET_DELAY_BETWEEN_SS … #define DLN2_SPI_SET_DELAY_AFTER_SS … #define DLN2_SPI_GET_DELAY_AFTER_SS … #define DLN2_SPI_SET_DELAY_BETWEEN_FRAMES … #define DLN2_SPI_GET_DELAY_BETWEEN_FRAMES … #define DLN2_SPI_SET_SS … #define DLN2_SPI_GET_SS … #define DLN2_SPI_RELEASE_SS … #define DLN2_SPI_SS_VARIABLE_ENABLE … #define DLN2_SPI_SS_VARIABLE_DISABLE … #define DLN2_SPI_SS_VARIABLE_IS_ENABLED … #define DLN2_SPI_SS_AAT_ENABLE … #define DLN2_SPI_SS_AAT_DISABLE … #define DLN2_SPI_SS_AAT_IS_ENABLED … #define DLN2_SPI_SS_BETWEEN_FRAMES_ENABLE … #define DLN2_SPI_SS_BETWEEN_FRAMES_DISABLE … #define DLN2_SPI_SS_BETWEEN_FRAMES_IS_ENABLED … #define DLN2_SPI_SET_CPHA … #define DLN2_SPI_GET_CPHA … #define DLN2_SPI_SET_CPOL … #define DLN2_SPI_GET_CPOL … #define DLN2_SPI_SS_MULTI_ENABLE … #define DLN2_SPI_SS_MULTI_DISABLE … #define DLN2_SPI_SS_MULTI_IS_ENABLED … #define DLN2_SPI_GET_SUPPORTED_MODES … #define DLN2_SPI_GET_SUPPORTED_CPHA_VALUES … #define DLN2_SPI_GET_SUPPORTED_CPOL_VALUES … #define DLN2_SPI_GET_SUPPORTED_FRAME_SIZES … #define DLN2_SPI_GET_SS_COUNT … #define DLN2_SPI_GET_MIN_FREQUENCY … #define DLN2_SPI_GET_MAX_FREQUENCY … #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_SS … #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_SS … #define DLN2_SPI_GET_MIN_DELAY_AFTER_SS … #define DLN2_SPI_GET_MAX_DELAY_AFTER_SS … #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_FRAMES … #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_FRAMES … #define DLN2_SPI_MAX_XFER_SIZE … #define DLN2_SPI_BUF_SIZE … #define DLN2_SPI_ATTR_LEAVE_SS_LOW … #define DLN2_TRANSFERS_WAIT_COMPLETE … #define DLN2_TRANSFERS_CANCEL … #define DLN2_RPM_AUTOSUSPEND_TIMEOUT … struct dln2_spi { … }; /* * Enable/Disable SPI module. The disable command will wait for transfers to * complete first. */ static int dln2_spi_enable(struct dln2_spi *dln2, bool enable) { … } /* * Select/unselect multiple CS lines. The selected lines will be automatically * toggled LOW/HIGH by the board firmware during transfers, provided they're * enabled first. * * Ex: cs_mask = 0x03 -> CS0 & CS1 will be selected and the next WR/RD operation * will toggle the lines LOW/HIGH automatically. */ static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask) { … } /* * Select one CS line. The other lines will be un-selected. */ static int dln2_spi_cs_set_one(struct dln2_spi *dln2, u8 cs) { … } /* * Enable/disable CS lines for usage. The module has to be disabled first. */ static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable) { … } static int dln2_spi_cs_enable_all(struct dln2_spi *dln2, bool enable) { … } static int dln2_spi_get_cs_num(struct dln2_spi *dln2, u16 *cs_num) { … } static int dln2_spi_get_speed(struct dln2_spi *dln2, u16 cmd, u32 *freq) { … } /* * Get bus min/max frequencies. */ static int dln2_spi_get_speed_range(struct dln2_spi *dln2, u32 *fmin, u32 *fmax) { … } /* * Set the bus speed. The module will automatically round down to the closest * available frequency and returns it. The module has to be disabled first. */ static int dln2_spi_set_speed(struct dln2_spi *dln2, u32 speed) { … } /* * Change CPOL & CPHA. The module has to be disabled first. */ static int dln2_spi_set_mode(struct dln2_spi *dln2, u8 mode) { … } /* * Change frame size. The module has to be disabled first. */ static int dln2_spi_set_bpw(struct dln2_spi *dln2, u8 bpw) { … } static int dln2_spi_get_supported_frame_sizes(struct dln2_spi *dln2, u32 *bpw_mask) { … } /* * Copy the data to DLN2 buffer and change the byte order to LE, requested by * DLN2 module. SPI core makes sure that the data length is a multiple of word * size. */ static int dln2_spi_copy_to_buf(u8 *dln2_buf, const u8 *src, u16 len, u8 bpw) { … } /* * Copy the data from DLN2 buffer and convert to CPU byte order since the DLN2 * buffer is LE ordered. SPI core makes sure that the data length is a multiple * of word size. The RX dln2_buf is 2 byte aligned so, for BE, we have to make * sure we avoid unaligned accesses for 32 bit case. */ static int dln2_spi_copy_from_buf(u8 *dest, const u8 *dln2_buf, u16 len, u8 bpw) { … } /* * Perform one write operation. */ static int dln2_spi_write_one(struct dln2_spi *dln2, const u8 *data, u16 data_len, u8 attr) { … } /* * Perform one read operation. */ static int dln2_spi_read_one(struct dln2_spi *dln2, u8 *data, u16 data_len, u8 attr) { … } /* * Perform one write & read operation. */ static int dln2_spi_read_write_one(struct dln2_spi *dln2, const u8 *tx_data, u8 *rx_data, u16 data_len, u8 attr) { … } /* * Read/Write wrapper. It will automatically split an operation into multiple * single ones due to device buffer constraints. */ static int dln2_spi_rdwr(struct dln2_spi *dln2, const u8 *tx_data, u8 *rx_data, u16 data_len, u8 attr) { … } static int dln2_spi_prepare_message(struct spi_controller *host, struct spi_message *message) { … } static int dln2_spi_transfer_setup(struct dln2_spi *dln2, u32 speed, u8 bpw, u8 mode) { … } static int dln2_spi_transfer_one(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *xfer) { … } static int dln2_spi_probe(struct platform_device *pdev) { … } static void dln2_spi_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int dln2_spi_suspend(struct device *dev) { … } static int dln2_spi_resume(struct device *dev) { … } #endif /* CONFIG_PM_SLEEP */ #ifdef CONFIG_PM static int dln2_spi_runtime_suspend(struct device *dev) { … } static int dln2_spi_runtime_resume(struct device *dev) { … } #endif /* CONFIG_PM */ static const struct dev_pm_ops dln2_spi_pm = …; static struct platform_driver spi_dln2_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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