// SPDX-License-Identifier: GPL-2.0+ /* * Freescale QuadSPI driver. * * Copyright (C) 2013 Freescale Semiconductor, Inc. * Copyright (C) 2018 Bootlin * Copyright (C) 2018 exceet electronics GmbH * Copyright (C) 2018 Kontron Electronics GmbH * * Transition to SPI MEM interface: * Authors: * Boris Brezillon <[email protected]> * Frieder Schrempf <[email protected]> * Yogesh Gaur <[email protected]> * Suresh Gupta <[email protected]> * * Based on the original fsl-quadspi.c SPI NOR driver: * Author: Freescale Semiconductor, Inc. * */ #include <linux/bitops.h> #include <linux/clk.h> #include <linux/completion.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/errno.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/jiffies.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_qos.h> #include <linux/sizes.h> #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> /* * The driver only uses one single LUT entry, that is updated on * each call of exec_op(). Index 0 is preset at boot with a basic * read operation, so let's use the last entry (15). */ #define SEQID_LUT … /* Registers used by the driver */ #define QUADSPI_MCR … #define QUADSPI_MCR_RESERVED_MASK … #define QUADSPI_MCR_MDIS_MASK … #define QUADSPI_MCR_CLR_TXF_MASK … #define QUADSPI_MCR_CLR_RXF_MASK … #define QUADSPI_MCR_DDR_EN_MASK … #define QUADSPI_MCR_END_CFG_MASK … #define QUADSPI_MCR_SWRSTHD_MASK … #define QUADSPI_MCR_SWRSTSD_MASK … #define QUADSPI_IPCR … #define QUADSPI_IPCR_SEQID(x) … #define QUADSPI_FLSHCR … #define QUADSPI_FLSHCR_TCSS_MASK … #define QUADSPI_FLSHCR_TCSH_MASK … #define QUADSPI_FLSHCR_TDH_MASK … #define QUADSPI_BUF0CR … #define QUADSPI_BUF1CR … #define QUADSPI_BUF2CR … #define QUADSPI_BUFXCR_INVALID_MSTRID … #define QUADSPI_BUF3CR … #define QUADSPI_BUF3CR_ALLMST_MASK … #define QUADSPI_BUF3CR_ADATSZ(x) … #define QUADSPI_BUF3CR_ADATSZ_MASK … #define QUADSPI_BFGENCR … #define QUADSPI_BFGENCR_SEQID(x) … #define QUADSPI_BUF0IND … #define QUADSPI_BUF1IND … #define QUADSPI_BUF2IND … #define QUADSPI_SFAR … #define QUADSPI_SMPR … #define QUADSPI_SMPR_DDRSMP_MASK … #define QUADSPI_SMPR_FSDLY_MASK … #define QUADSPI_SMPR_FSPHS_MASK … #define QUADSPI_SMPR_HSENA_MASK … #define QUADSPI_RBCT … #define QUADSPI_RBCT_WMRK_MASK … #define QUADSPI_RBCT_RXBRD_USEIPS … #define QUADSPI_TBDR … #define QUADSPI_SR … #define QUADSPI_SR_IP_ACC_MASK … #define QUADSPI_SR_AHB_ACC_MASK … #define QUADSPI_FR … #define QUADSPI_FR_TFF_MASK … #define QUADSPI_RSER … #define QUADSPI_RSER_TFIE … #define QUADSPI_SPTRCLR … #define QUADSPI_SPTRCLR_IPPTRC … #define QUADSPI_SPTRCLR_BFPTRC … #define QUADSPI_SFA1AD … #define QUADSPI_SFA2AD … #define QUADSPI_SFB1AD … #define QUADSPI_SFB2AD … #define QUADSPI_RBDR(x) … #define QUADSPI_LUTKEY … #define QUADSPI_LUTKEY_VALUE … #define QUADSPI_LCKCR … #define QUADSPI_LCKER_LOCK … #define QUADSPI_LCKER_UNLOCK … #define QUADSPI_LUT_BASE … #define QUADSPI_LUT_OFFSET … #define QUADSPI_LUT_REG(idx) … /* Instruction set for the LUT register */ #define LUT_STOP … #define LUT_CMD … #define LUT_ADDR … #define LUT_DUMMY … #define LUT_MODE … #define LUT_MODE2 … #define LUT_MODE4 … #define LUT_FSL_READ … #define LUT_FSL_WRITE … #define LUT_JMP_ON_CS … #define LUT_ADDR_DDR … #define LUT_MODE_DDR … #define LUT_MODE2_DDR … #define LUT_MODE4_DDR … #define LUT_FSL_READ_DDR … #define LUT_FSL_WRITE_DDR … #define LUT_DATA_LEARN … /* * The PAD definitions for LUT register. * * The pad stands for the number of IO lines [0:3]. * For example, the quad read needs four IO lines, * so you should use LUT_PAD(4). */ #define LUT_PAD(x) … /* * Macro for constructing the LUT entries with the following * register layout: * * --------------------------------------------------- * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | * --------------------------------------------------- */ #define LUT_DEF(idx, ins, pad, opr) … /* Controller needs driver to swap endianness */ #define QUADSPI_QUIRK_SWAP_ENDIAN … /* Controller needs 4x internal clock */ #define QUADSPI_QUIRK_4X_INT_CLK … /* * TKT253890, the controller needs the driver to fill the txfifo with * 16 bytes at least to trigger a data transfer, even though the extra * data won't be transferred. */ #define QUADSPI_QUIRK_TKT253890 … /* TKT245618, the controller cannot wake up from wait mode */ #define QUADSPI_QUIRK_TKT245618 … /* * Controller adds QSPI_AMBA_BASE (base address of the mapped memory) * internally. No need to add it when setting SFXXAD and SFAR registers */ #define QUADSPI_QUIRK_BASE_INTERNAL … /* * Controller uses TDH bits in register QUADSPI_FLSHCR. * They need to be set in accordance with the DDR/SDR mode. */ #define QUADSPI_QUIRK_USE_TDH_SETTING … struct fsl_qspi_devtype_data { … }; static const struct fsl_qspi_devtype_data vybrid_data = …; static const struct fsl_qspi_devtype_data imx6sx_data = …; static const struct fsl_qspi_devtype_data imx7d_data = …; static const struct fsl_qspi_devtype_data imx6ul_data = …; static const struct fsl_qspi_devtype_data ls1021a_data = …; static const struct fsl_qspi_devtype_data ls2080a_data = …; struct fsl_qspi { … }; static inline int needs_swap_endian(struct fsl_qspi *q) { … } static inline int needs_4x_clock(struct fsl_qspi *q) { … } static inline int needs_fill_txfifo(struct fsl_qspi *q) { … } static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) { … } static inline int needs_amba_base_offset(struct fsl_qspi *q) { … } static inline int needs_tdh_setting(struct fsl_qspi *q) { … } /* * An IC bug makes it necessary to rearrange the 32-bit data. * Later chips, such as IMX6SLX, have fixed this bug. */ static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) { … } /* * R/W functions for big- or little-endian registers: * The QSPI controller's endianness is independent of * the CPU core's endianness. So far, although the CPU * core is little-endian the QSPI controller can use * big-endian or little-endian. */ static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr) { … } static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) { … } static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id) { … } static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) { … } static bool fsl_qspi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static void fsl_qspi_prepare_lut(struct fsl_qspi *q, const struct spi_mem_op *op) { … } static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q) { … } static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q) { … } /* * If we have changed the content of the flash by writing or erasing, or if we * read from flash with a different offset into the page buffer, we need to * invalidate the AHB buffer. If we do not do so, we may read out the wrong * data. The spec tells us reset the AHB domain and Serial Flash domain at * the same time. */ static void fsl_qspi_invalidate(struct fsl_qspi *q) { … } static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi) { … } static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op) { … } static void fsl_qspi_fill_txfifo(struct fsl_qspi *q, const struct spi_mem_op *op) { … } static void fsl_qspi_read_rxfifo(struct fsl_qspi *q, const struct spi_mem_op *op) { … } static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op) { … } static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base, u32 mask, u32 delay_us, u32 timeout_us) { … } static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) { … } static int fsl_qspi_default_setup(struct fsl_qspi *q) { … } static const char *fsl_qspi_get_name(struct spi_mem *mem) { … } static const struct spi_controller_mem_ops fsl_qspi_mem_ops = …; static int fsl_qspi_probe(struct platform_device *pdev) { … } static void fsl_qspi_remove(struct platform_device *pdev) { … } static int fsl_qspi_suspend(struct device *dev) { … } static int fsl_qspi_resume(struct device *dev) { … } static const struct of_device_id fsl_qspi_dt_ids[] = …; MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids); static const struct dev_pm_ops fsl_qspi_pm_ops = …; static struct platform_driver fsl_qspi_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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