/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Freescale SPI controller driver. * * Maintainer: Kumar Gala * * Copyright (C) 2006 Polycom, Inc. * Copyright 2010 Freescale Semiconductor, Inc. * * CPM SPI and QE buffer descriptors mode support: * Copyright (c) 2009 MontaVista Software, Inc. * Author: Anton Vorontsov <[email protected]> * * GRLIB support: * Copyright (c) 2012 Aeroflex Gaisler AB. * Author: Andreas Larsson <[email protected]> */ #ifndef __SPI_FSL_SPI_H__ #define __SPI_FSL_SPI_H__ /* SPI Controller registers */ struct fsl_spi_reg { … }; /* SPI Controller mode register definitions */ #define SPMODE_LOOP … #define SPMODE_CI_INACTIVEHIGH … #define SPMODE_CP_BEGIN_EDGECLK … #define SPMODE_DIV16 … #define SPMODE_REV … #define SPMODE_MS … #define SPMODE_ENABLE … #define SPMODE_LEN(x) … #define SPMODE_PM(x) … #define SPMODE_OP … #define SPMODE_CG(x) … /* TYPE_GRLIB SPI Controller capability register definitions */ #define SPCAP_SSEN(x) … #define SPCAP_SSSZ(x) … #define SPCAP_MAXWLEN(x) … /* * Default for SPI Mode: * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk */ #define SPMODE_INIT_VAL … /* SPIE register values */ #define SPIE_NE … #define SPIE_NF … /* SPIM register values */ #define SPIM_NE … #define SPIM_NF … #endif /* __SPI_FSL_SPI_H__ */
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