// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2011-2015 Daniel Schwierzeck <[email protected]> * Copyright (C) 2016 Hauke Mehrtens <[email protected]> */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/io.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/sched.h> #include <linux/completion.h> #include <linux/spinlock.h> #include <linux/err.h> #include <linux/pm_runtime.h> #include <linux/spi/spi.h> #ifdef CONFIG_LANTIQ #include <lantiq_soc.h> #endif #define LTQ_SPI_RX_IRQ_NAME … #define LTQ_SPI_TX_IRQ_NAME … #define LTQ_SPI_ERR_IRQ_NAME … #define LTQ_SPI_FRM_IRQ_NAME … #define LTQ_SPI_CLC … #define LTQ_SPI_PISEL … #define LTQ_SPI_ID … #define LTQ_SPI_CON … #define LTQ_SPI_STAT … #define LTQ_SPI_WHBSTATE … #define LTQ_SPI_TB … #define LTQ_SPI_RB … #define LTQ_SPI_RXFCON … #define LTQ_SPI_TXFCON … #define LTQ_SPI_FSTAT … #define LTQ_SPI_BRT … #define LTQ_SPI_BRSTAT … #define LTQ_SPI_SFCON … #define LTQ_SPI_SFSTAT … #define LTQ_SPI_GPOCON … #define LTQ_SPI_GPOSTAT … #define LTQ_SPI_FPGO … #define LTQ_SPI_RXREQ … #define LTQ_SPI_RXCNT … #define LTQ_SPI_DMACON … #define LTQ_SPI_IRNEN … #define LTQ_SPI_CLC_SMC_S … #define LTQ_SPI_CLC_SMC_M … #define LTQ_SPI_CLC_RMC_S … #define LTQ_SPI_CLC_RMC_M … #define LTQ_SPI_CLC_DISS … #define LTQ_SPI_CLC_DISR … #define LTQ_SPI_ID_TXFS_S … #define LTQ_SPI_ID_RXFS_S … #define LTQ_SPI_ID_MOD_S … #define LTQ_SPI_ID_MOD_M … #define LTQ_SPI_ID_CFG_S … #define LTQ_SPI_ID_CFG_M … #define LTQ_SPI_ID_REV_M … #define LTQ_SPI_CON_BM_S … #define LTQ_SPI_CON_BM_M … #define LTQ_SPI_CON_EM … #define LTQ_SPI_CON_IDLE … #define LTQ_SPI_CON_ENBV … #define LTQ_SPI_CON_RUEN … #define LTQ_SPI_CON_TUEN … #define LTQ_SPI_CON_AEN … #define LTQ_SPI_CON_REN … #define LTQ_SPI_CON_TEN … #define LTQ_SPI_CON_LB … #define LTQ_SPI_CON_PO … #define LTQ_SPI_CON_PH … #define LTQ_SPI_CON_HB … #define LTQ_SPI_CON_RXOFF … #define LTQ_SPI_CON_TXOFF … #define LTQ_SPI_STAT_RXBV_S … #define LTQ_SPI_STAT_RXBV_M … #define LTQ_SPI_STAT_BSY … #define LTQ_SPI_STAT_RUE … #define LTQ_SPI_STAT_TUE … #define LTQ_SPI_STAT_AE … #define LTQ_SPI_STAT_RE … #define LTQ_SPI_STAT_TE … #define LTQ_SPI_STAT_ME … #define LTQ_SPI_STAT_MS … #define LTQ_SPI_STAT_EN … #define LTQ_SPI_STAT_ERRORS … #define LTQ_SPI_WHBSTATE_SETTUE … #define LTQ_SPI_WHBSTATE_SETAE … #define LTQ_SPI_WHBSTATE_SETRE … #define LTQ_SPI_WHBSTATE_SETTE … #define LTQ_SPI_WHBSTATE_CLRTUE … #define LTQ_SPI_WHBSTATE_CLRAE … #define LTQ_SPI_WHBSTATE_CLRRE … #define LTQ_SPI_WHBSTATE_CLRTE … #define LTQ_SPI_WHBSTATE_SETME … #define LTQ_SPI_WHBSTATE_CLRME … #define LTQ_SPI_WHBSTATE_SETRUE … #define LTQ_SPI_WHBSTATE_CLRRUE … #define LTQ_SPI_WHBSTATE_SETMS … #define LTQ_SPI_WHBSTATE_CLRMS … #define LTQ_SPI_WHBSTATE_SETEN … #define LTQ_SPI_WHBSTATE_CLREN … #define LTQ_SPI_WHBSTATE_CLR_ERRORS … #define LTQ_SPI_RXFCON_RXFITL_S … #define LTQ_SPI_RXFCON_RXFLU … #define LTQ_SPI_RXFCON_RXFEN … #define LTQ_SPI_TXFCON_TXFITL_S … #define LTQ_SPI_TXFCON_TXFLU … #define LTQ_SPI_TXFCON_TXFEN … #define LTQ_SPI_FSTAT_RXFFL_S … #define LTQ_SPI_FSTAT_TXFFL_S … #define LTQ_SPI_GPOCON_ISCSBN_S … #define LTQ_SPI_GPOCON_INVOUTN_S … #define LTQ_SPI_FGPO_SETOUTN_S … #define LTQ_SPI_FGPO_CLROUTN_S … #define LTQ_SPI_RXREQ_RXCNT_M … #define LTQ_SPI_RXCNT_TODO_M … #define LTQ_SPI_IRNEN_TFI … #define LTQ_SPI_IRNEN_F … #define LTQ_SPI_IRNEN_E … #define LTQ_SPI_IRNEN_T_XWAY … #define LTQ_SPI_IRNEN_R_XWAY … #define LTQ_SPI_IRNEN_R_XRX … #define LTQ_SPI_IRNEN_T_XRX … #define LTQ_SPI_IRNEN_ALL … struct lantiq_ssc_spi; struct lantiq_ssc_hwcfg { … }; struct lantiq_ssc_spi { … }; static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg) { … } static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val, u32 reg) { … } static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr, u32 set, u32 reg) { … } static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi) { … } static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi) { … } static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi) { … } static void rx_fifo_reset(const struct lantiq_ssc_spi *spi) { … } static void tx_fifo_reset(const struct lantiq_ssc_spi *spi) { … } static void rx_fifo_flush(const struct lantiq_ssc_spi *spi) { … } static void tx_fifo_flush(const struct lantiq_ssc_spi *spi) { … } static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi) { … } static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi) { … } static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi, unsigned int max_speed_hz) { … } static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi, unsigned int bits_per_word) { … } static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi, unsigned int mode) { … } static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi) { … } static int lantiq_ssc_setup(struct spi_device *spidev) { … } static int lantiq_ssc_prepare_message(struct spi_controller *host, struct spi_message *message) { … } static void hw_setup_transfer(struct lantiq_ssc_spi *spi, struct spi_device *spidev, struct spi_transfer *t) { … } static int lantiq_ssc_unprepare_message(struct spi_controller *host, struct spi_message *message) { … } static void tx_fifo_write(struct lantiq_ssc_spi *spi) { … } static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi) { … } static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi) { … } static void rx_request(struct lantiq_ssc_spi *spi) { … } static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data) { … } static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data) { … } static irqreturn_t intel_lgm_ssc_isr(int irq, void *data) { … } static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev, struct spi_transfer *t) { … } /* * The driver only gets an interrupt when the FIFO is empty, but there * is an additional shift register from which the data is written to * the wire. We get the last interrupt when the controller starts to * write the last word to the wire, not when it is finished. Do busy * waiting till it finishes. */ static void lantiq_ssc_bussy_work(struct work_struct *work) { … } static void lantiq_ssc_handle_err(struct spi_controller *host, struct spi_message *message) { … } static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable) { … } static int lantiq_ssc_transfer_one(struct spi_controller *host, struct spi_device *spidev, struct spi_transfer *t) { … } static int intel_lgm_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi) { … } static int lantiq_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi) { … } static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = …; static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = …; static const struct lantiq_ssc_hwcfg intel_ssc_lgm = …; static const struct of_device_id lantiq_ssc_match[] = …; MODULE_DEVICE_TABLE(of, lantiq_ssc_match); static int lantiq_ssc_probe(struct platform_device *pdev) { … } static void lantiq_ssc_remove(struct platform_device *pdev) { … } static struct platform_driver lantiq_ssc_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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