// SPDX-License-Identifier: GPL-2.0-only /* * Intel PCH/PCU SPI flash driver. * * Copyright (C) 2016 - 2022, Intel Corporation * Author: Mika Westerberg <[email protected]> */ #include <linux/iopoll.h> #include <linux/module.h> #include <linux/mtd/partitions.h> #include <linux/mtd/spi-nor.h> #include <linux/spi/flash.h> #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> #include "spi-intel.h" /* Offsets are from @ispi->base */ #define BFPREG … #define HSFSTS_CTL … #define HSFSTS_CTL_FSMIE … #define HSFSTS_CTL_FDBC_SHIFT … #define HSFSTS_CTL_FDBC_MASK … #define HSFSTS_CTL_FCYCLE_SHIFT … #define HSFSTS_CTL_FCYCLE_MASK … /* HW sequencer opcodes */ #define HSFSTS_CTL_FCYCLE_READ … #define HSFSTS_CTL_FCYCLE_WRITE … #define HSFSTS_CTL_FCYCLE_ERASE … #define HSFSTS_CTL_FCYCLE_ERASE_64K … #define HSFSTS_CTL_FCYCLE_RDSFDP … #define HSFSTS_CTL_FCYCLE_RDID … #define HSFSTS_CTL_FCYCLE_WRSR … #define HSFSTS_CTL_FCYCLE_RDSR … #define HSFSTS_CTL_FGO … #define HSFSTS_CTL_FLOCKDN … #define HSFSTS_CTL_FDV … #define HSFSTS_CTL_SCIP … #define HSFSTS_CTL_AEL … #define HSFSTS_CTL_FCERR … #define HSFSTS_CTL_FDONE … #define FADDR … #define DLOCK … #define FDATA(n) … #define FRACC … #define FREG(n) … #define FREG_BASE_MASK … #define FREG_LIMIT_SHIFT … #define FREG_LIMIT_MASK … /* Offset is from @ispi->pregs */ #define PR(n) … #define PR_WPE … #define PR_LIMIT_SHIFT … #define PR_LIMIT_MASK … #define PR_RPE … #define PR_BASE_MASK … /* Offsets are from @ispi->sregs */ #define SSFSTS_CTL … #define SSFSTS_CTL_FSMIE … #define SSFSTS_CTL_DS … #define SSFSTS_CTL_DBC_SHIFT … #define SSFSTS_CTL_SPOP … #define SSFSTS_CTL_ACS … #define SSFSTS_CTL_SCGO … #define SSFSTS_CTL_COP_SHIFT … #define SSFSTS_CTL_FRS … #define SSFSTS_CTL_DOFRS … #define SSFSTS_CTL_AEL … #define SSFSTS_CTL_FCERR … #define SSFSTS_CTL_FDONE … #define SSFSTS_CTL_SCIP … #define PREOP_OPTYPE … #define OPMENU0 … #define OPMENU1 … #define OPTYPE_READ_NO_ADDR … #define OPTYPE_WRITE_NO_ADDR … #define OPTYPE_READ_WITH_ADDR … #define OPTYPE_WRITE_WITH_ADDR … /* CPU specifics */ #define BYT_PR … #define BYT_SSFSTS_CTL … #define BYT_FREG_NUM … #define BYT_PR_NUM … #define LPT_PR … #define LPT_SSFSTS_CTL … #define LPT_FREG_NUM … #define LPT_PR_NUM … #define BXT_PR … #define BXT_SSFSTS_CTL … #define BXT_FREG_NUM … #define BXT_PR_NUM … #define CNL_PR … #define CNL_FREG_NUM … #define CNL_PR_NUM … #define LVSCC … #define UVSCC … #define ERASE_OPCODE_SHIFT … #define ERASE_OPCODE_MASK … #define ERASE_64K_OPCODE_SHIFT … #define ERASE_64K_OPCODE_MASK … /* Flash descriptor fields */ #define FLVALSIG_MAGIC … #define FLMAP0_NC_MASK … #define FLMAP0_NC_SHIFT … #define FLMAP0_FCBA_MASK … #define FLCOMP_C0DEN_MASK … #define FLCOMP_C0DEN_512K … #define FLCOMP_C0DEN_1M … #define FLCOMP_C0DEN_2M … #define FLCOMP_C0DEN_4M … #define FLCOMP_C0DEN_8M … #define FLCOMP_C0DEN_16M … #define FLCOMP_C0DEN_32M … #define FLCOMP_C0DEN_64M … #define INTEL_SPI_TIMEOUT … #define INTEL_SPI_FIFO_SZ … /** * struct intel_spi - Driver private data * @dev: Device pointer * @info: Pointer to board specific info * @base: Beginning of MMIO space * @pregs: Start of protection registers * @sregs: Start of software sequencer registers * @host: Pointer to the SPI controller structure * @nregions: Maximum number of regions * @pr_num: Maximum number of protected range registers * @chip0_size: Size of the first flash chip in bytes * @locked: Is SPI setting locked * @swseq_reg: Use SW sequencer in register reads/writes * @swseq_erase: Use SW sequencer in erase operation * @atomic_preopcode: Holds preopcode when atomic sequence is requested * @opcodes: Opcodes which are supported. This are programmed by BIOS * before it locks down the controller. * @mem_ops: Pointer to SPI MEM ops supported by the controller */ struct intel_spi { … }; struct intel_spi_mem_op { … }; static bool writeable; module_param(writeable, bool, 0); MODULE_PARM_DESC(…) …; static void intel_spi_dump_regs(struct intel_spi *ispi) { … } /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */ static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size) { … } /* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */ static int intel_spi_write_block(struct intel_spi *ispi, const void *buf, size_t size) { … } static int intel_spi_wait_hw_busy(struct intel_spi *ispi) { … } static int intel_spi_wait_sw_busy(struct intel_spi *ispi) { … } static bool intel_spi_set_writeable(struct intel_spi *ispi) { … } static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype) { … } static int intel_spi_hw_cycle(struct intel_spi *ispi, const struct intel_spi_mem_op *iop, size_t len) { … } static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len, int optype) { … } static u32 intel_spi_chip_addr(const struct intel_spi *ispi, const struct spi_mem *mem) { … } static int intel_spi_read_reg(struct intel_spi *ispi, const struct spi_mem *mem, const struct intel_spi_mem_op *iop, const struct spi_mem_op *op) { … } static int intel_spi_write_reg(struct intel_spi *ispi, const struct spi_mem *mem, const struct intel_spi_mem_op *iop, const struct spi_mem_op *op) { … } static int intel_spi_read(struct intel_spi *ispi, const struct spi_mem *mem, const struct intel_spi_mem_op *iop, const struct spi_mem_op *op) { … } static int intel_spi_write(struct intel_spi *ispi, const struct spi_mem *mem, const struct intel_spi_mem_op *iop, const struct spi_mem_op *op) { … } static int intel_spi_erase(struct intel_spi *ispi, const struct spi_mem *mem, const struct intel_spi_mem_op *iop, const struct spi_mem_op *op) { … } static int intel_spi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) { … } static bool intel_spi_cmp_mem_op(const struct intel_spi_mem_op *iop, const struct spi_mem_op *op) { … } static const struct intel_spi_mem_op * intel_spi_match_mem_op(struct intel_spi *ispi, const struct spi_mem_op *op) { … } static bool intel_spi_supports_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static int intel_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static const char *intel_spi_get_name(struct spi_mem *mem) { … } static int intel_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) { … } static ssize_t intel_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf) { … } static ssize_t intel_spi_dirmap_write(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, const void *buf) { … } static const struct spi_controller_mem_ops intel_spi_mem_ops = …; #define INTEL_SPI_OP_ADDR(__nbytes) … #define INTEL_SPI_OP_NO_DATA … #define INTEL_SPI_OP_DATA_IN(__buswidth) … #define INTEL_SPI_OP_DATA_OUT(__buswidth) … #define INTEL_SPI_MEM_OP(__cmd, __addr, __data, __exec_op) … #define INTEL_SPI_MEM_OP_REPL(__cmd, __addr, __data, __exec_op, __repl) … /* * The controller handles pretty much everything internally based on the * SFDP data but we want to make sure we only support the operations * actually possible. Only check buswidth and transfer direction, the * core validates data. */ #define INTEL_SPI_GENERIC_OPS … \ static const struct intel_spi_mem_op generic_mem_ops[] = …; static const struct intel_spi_mem_op erase_64k_mem_ops[] = …; static int intel_spi_init(struct intel_spi *ispi) { … } static bool intel_spi_is_protected(const struct intel_spi *ispi, unsigned int base, unsigned int limit) { … } /* * There will be a single partition holding all enabled flash regions. We * call this "BIOS". */ static void intel_spi_fill_partition(struct intel_spi *ispi, struct mtd_partition *part) { … } static int intel_spi_read_desc(struct intel_spi *ispi) { … } static int intel_spi_populate_chip(struct intel_spi *ispi) { … } /** * intel_spi_probe() - Probe the Intel SPI flash controller * @dev: Pointer to the parent device * @mem: MMIO resource * @info: Platform specific information * * Probes Intel SPI flash controller and creates the flash chip device. * Returns %0 on success and negative errno in case of failure. */ int intel_spi_probe(struct device *dev, struct resource *mem, const struct intel_spi_boardinfo *info) { … } EXPORT_SYMBOL_GPL(…); MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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