// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015 MediaTek Inc. * Author: Leilk Liu <[email protected]> */ #include <linux/clk.h> #include <linux/device.h> #include <linux/err.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/ioport.h> #include <linux/module.h> #include <linux/of.h> #include <linux/gpio/consumer.h> #include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> #include <linux/platform_data/spi-mt65xx.h> #include <linux/pm_runtime.h> #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> #include <linux/dma-mapping.h> #define SPI_CFG0_REG … #define SPI_CFG1_REG … #define SPI_TX_SRC_REG … #define SPI_RX_DST_REG … #define SPI_TX_DATA_REG … #define SPI_RX_DATA_REG … #define SPI_CMD_REG … #define SPI_STATUS0_REG … #define SPI_PAD_SEL_REG … #define SPI_CFG2_REG … #define SPI_TX_SRC_REG_64 … #define SPI_RX_DST_REG_64 … #define SPI_CFG3_IPM_REG … #define SPI_CFG0_SCK_HIGH_OFFSET … #define SPI_CFG0_SCK_LOW_OFFSET … #define SPI_CFG0_CS_HOLD_OFFSET … #define SPI_CFG0_CS_SETUP_OFFSET … #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET … #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET … #define SPI_CFG1_CS_IDLE_OFFSET … #define SPI_CFG1_PACKET_LOOP_OFFSET … #define SPI_CFG1_PACKET_LENGTH_OFFSET … #define SPI_CFG1_GET_TICK_DLY_OFFSET … #define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 … #define SPI_CFG1_GET_TICK_DLY_MASK … #define SPI_CFG1_GET_TICK_DLY_MASK_V1 … #define SPI_CFG1_CS_IDLE_MASK … #define SPI_CFG1_PACKET_LOOP_MASK … #define SPI_CFG1_PACKET_LENGTH_MASK … #define SPI_CFG1_IPM_PACKET_LENGTH_MASK … #define SPI_CFG2_SCK_HIGH_OFFSET … #define SPI_CFG2_SCK_LOW_OFFSET … #define SPI_CMD_ACT … #define SPI_CMD_RESUME … #define SPI_CMD_RST … #define SPI_CMD_PAUSE_EN … #define SPI_CMD_DEASSERT … #define SPI_CMD_SAMPLE_SEL … #define SPI_CMD_CS_POL … #define SPI_CMD_CPHA … #define SPI_CMD_CPOL … #define SPI_CMD_RX_DMA … #define SPI_CMD_TX_DMA … #define SPI_CMD_TXMSBF … #define SPI_CMD_RXMSBF … #define SPI_CMD_RX_ENDIAN … #define SPI_CMD_TX_ENDIAN … #define SPI_CMD_FINISH_IE … #define SPI_CMD_PAUSE_IE … #define SPI_CMD_IPM_NONIDLE_MODE … #define SPI_CMD_IPM_SPIM_LOOP … #define SPI_CMD_IPM_GET_TICKDLY_OFFSET … #define SPI_CMD_IPM_GET_TICKDLY_MASK … #define PIN_MODE_CFG(x) … #define SPI_CFG3_IPM_HALF_DUPLEX_DIR … #define SPI_CFG3_IPM_HALF_DUPLEX_EN … #define SPI_CFG3_IPM_XMODE_EN … #define SPI_CFG3_IPM_NODATA_FLAG … #define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET … #define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET … #define SPI_CFG3_IPM_CMD_PIN_MODE_MASK … #define SPI_CFG3_IPM_CMD_BYTELEN_MASK … #define SPI_CFG3_IPM_ADDR_BYTELEN_MASK … #define MT8173_SPI_MAX_PAD_SEL … #define MTK_SPI_PAUSE_INT_STATUS … #define MTK_SPI_MAX_FIFO_SIZE … #define MTK_SPI_PACKET_SIZE … #define MTK_SPI_IPM_PACKET_SIZE … #define MTK_SPI_IPM_PACKET_LOOP … #define MTK_SPI_IDLE … #define MTK_SPI_PAUSED … #define MTK_SPI_32BITS_MASK … #define DMA_ADDR_EXT_BITS … #define DMA_ADDR_DEF_BITS … /** * struct mtk_spi_compatible - device data structure * @need_pad_sel: Enable pad (pins) selection in SPI controller * @must_tx: Must explicitly send dummy TX bytes to do RX only transfer * @enhance_timing: Enable adjusting cfg register to enhance time accuracy * @dma_ext: DMA address extension supported * @no_need_unprepare: Don't unprepare the SPI clk during runtime * @ipm_design: Adjust/extend registers to support IPM design IP features */ struct mtk_spi_compatible { … }; /** * struct mtk_spi - SPI driver instance * @base: Start address of the SPI controller registers * @state: SPI controller state * @pad_num: Number of pad_sel entries * @pad_sel: Groups of pins to select * @parent_clk: Parent of sel_clk * @sel_clk: SPI host mux clock * @spi_clk: Peripheral clock * @spi_hclk: AHB bus clock * @cur_transfer: Currently processed SPI transfer * @xfer_len: Number of bytes to transfer * @num_xfered: Number of transferred bytes * @tx_sgl: TX transfer scatterlist * @rx_sgl: RX transfer scatterlist * @tx_sgl_len: Size of TX DMA transfer * @rx_sgl_len: Size of RX DMA transfer * @dev_comp: Device data structure * @spi_clk_hz: Current SPI clock in Hz * @spimem_done: SPI-MEM operation completion * @use_spimem: Enables SPI-MEM * @dev: Device pointer * @tx_dma: DMA start for SPI-MEM TX * @rx_dma: DMA start for SPI-MEM RX */ struct mtk_spi { … }; static const struct mtk_spi_compatible mtk_common_compat; static const struct mtk_spi_compatible mt2712_compat = …; static const struct mtk_spi_compatible mtk_ipm_compat = …; static const struct mtk_spi_compatible mt6765_compat = …; static const struct mtk_spi_compatible mt7622_compat = …; static const struct mtk_spi_compatible mt8173_compat = …; static const struct mtk_spi_compatible mt8183_compat = …; static const struct mtk_spi_compatible mt6893_compat = …; /* * A piece of default chip info unless the platform * supplies it. */ static const struct mtk_chip_config mtk_default_chip_info = …; static const struct of_device_id mtk_spi_of_match[] = …; MODULE_DEVICE_TABLE(of, mtk_spi_of_match); static void mtk_spi_reset(struct mtk_spi *mdata) { … } static int mtk_spi_set_hw_cs_timing(struct spi_device *spi) { … } static int mtk_spi_hw_init(struct spi_controller *host, struct spi_device *spi) { … } static int mtk_spi_prepare_message(struct spi_controller *host, struct spi_message *msg) { … } static void mtk_spi_set_cs(struct spi_device *spi, bool enable) { … } static void mtk_spi_prepare_transfer(struct spi_controller *host, u32 speed_hz) { … } static void mtk_spi_setup_packet(struct spi_controller *host) { … } static void mtk_spi_enable_transfer(struct spi_controller *host) { … } static int mtk_spi_get_mult_delta(struct mtk_spi *mdata, u32 xfer_len) { … } static void mtk_spi_update_mdata_len(struct spi_controller *host) { … } static void mtk_spi_setup_dma_addr(struct spi_controller *host, struct spi_transfer *xfer) { … } static int mtk_spi_fifo_transfer(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *xfer) { … } static int mtk_spi_dma_transfer(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *xfer) { … } static int mtk_spi_transfer_one(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *xfer) { … } static bool mtk_spi_can_dma(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *xfer) { … } static int mtk_spi_setup(struct spi_device *spi) { … } static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) { … } static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) { … } static bool mtk_spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static void mtk_spi_mem_setup_dma_xfer(struct spi_controller *host, const struct spi_mem_op *op) { … } static int mtk_spi_transfer_wait(struct spi_mem *mem, const struct spi_mem_op *op) { … } static int mtk_spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static const struct spi_controller_mem_ops mtk_spi_mem_ops = …; static int mtk_spi_probe(struct platform_device *pdev) { … } static void mtk_spi_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int mtk_spi_suspend(struct device *dev) { … } static int mtk_spi_resume(struct device *dev) { … } #endif /* CONFIG_PM_SLEEP */ #ifdef CONFIG_PM static int mtk_spi_runtime_suspend(struct device *dev) { … } static int mtk_spi_runtime_resume(struct device *dev) { … } #endif /* CONFIG_PM */ static const struct dev_pm_ops mtk_spi_pm = …; static struct platform_driver mtk_spi_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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