// SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2019 Nuvoton Technology corporation. #include <linux/bits.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/device.h> #include <linux/module.h> #include <linux/ioport.h> #include <linux/clk.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/vmalloc.h> #include <linux/regmap.h> #include <linux/of.h> #include <linux/spi/spi-mem.h> #include <linux/mfd/syscon.h> /* NPCM7xx GCR module */ #define NPCM7XX_INTCR3_OFFSET … #define NPCM7XX_INTCR3_FIU_FIX … /* Flash Interface Unit (FIU) Registers */ #define NPCM_FIU_DRD_CFG … #define NPCM_FIU_DWR_CFG … #define NPCM_FIU_UMA_CFG … #define NPCM_FIU_UMA_CTS … #define NPCM_FIU_UMA_CMD … #define NPCM_FIU_UMA_ADDR … #define NPCM_FIU_PRT_CFG … #define NPCM_FIU_UMA_DW0 … #define NPCM_FIU_UMA_DW1 … #define NPCM_FIU_UMA_DW2 … #define NPCM_FIU_UMA_DW3 … #define NPCM_FIU_UMA_DR0 … #define NPCM_FIU_UMA_DR1 … #define NPCM_FIU_UMA_DR2 … #define NPCM_FIU_UMA_DR3 … #define NPCM_FIU_CFG … #define NPCM_FIU_MAX_REG_LIMIT … /* FIU Direct Read Configuration Register */ #define NPCM_FIU_DRD_CFG_LCK … #define NPCM_FIU_DRD_CFG_R_BURST … #define NPCM_FIU_DRD_CFG_ADDSIZ … #define NPCM_FIU_DRD_CFG_DBW … #define NPCM_FIU_DRD_CFG_ACCTYPE … #define NPCM_FIU_DRD_CFG_RDCMD … #define NPCM_FIU_DRD_ADDSIZ_SHIFT … #define NPCM_FIU_DRD_DBW_SHIFT … #define NPCM_FIU_DRD_ACCTYPE_SHIFT … /* FIU Direct Write Configuration Register */ #define NPCM_FIU_DWR_CFG_LCK … #define NPCM_FIU_DWR_CFG_W_BURST … #define NPCM_FIU_DWR_CFG_ADDSIZ … #define NPCM_FIU_DWR_CFG_ABPCK … #define NPCM_FIU_DWR_CFG_DBPCK … #define NPCM_FIU_DWR_CFG_WRCMD … #define NPCM_FIU_DWR_ADDSIZ_SHIFT … #define NPCM_FIU_DWR_ABPCK_SHIFT … #define NPCM_FIU_DWR_DBPCK_SHIFT … /* FIU UMA Configuration Register */ #define NPCM_FIU_UMA_CFG_LCK … #define NPCM_FIU_UMA_CFG_CMMLCK … #define NPCM_FIU_UMA_CFG_RDATSIZ … #define NPCM_FIU_UMA_CFG_DBSIZ … #define NPCM_FIU_UMA_CFG_WDATSIZ … #define NPCM_FIU_UMA_CFG_ADDSIZ … #define NPCM_FIU_UMA_CFG_CMDSIZ … #define NPCM_FIU_UMA_CFG_RDBPCK … #define NPCM_FIU_UMA_CFG_DBPCK … #define NPCM_FIU_UMA_CFG_WDBPCK … #define NPCM_FIU_UMA_CFG_ADBPCK … #define NPCM_FIU_UMA_CFG_CMBPCK … #define NPCM_FIU_UMA_CFG_ADBPCK_SHIFT … #define NPCM_FIU_UMA_CFG_WDBPCK_SHIFT … #define NPCM_FIU_UMA_CFG_DBPCK_SHIFT … #define NPCM_FIU_UMA_CFG_RDBPCK_SHIFT … #define NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT … #define NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT … #define NPCM_FIU_UMA_CFG_DBSIZ_SHIFT … #define NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT … /* FIU UMA Control and Status Register */ #define NPCM_FIU_UMA_CTS_RDYIE … #define NPCM_FIU_UMA_CTS_RDYST … #define NPCM_FIU_UMA_CTS_SW_CS … #define NPCM_FIU_UMA_CTS_DEV_NUM … #define NPCM_FIU_UMA_CTS_EXEC_DONE … #define NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT … /* FIU UMA Command Register */ #define NPCM_FIU_UMA_CMD_DUM3 … #define NPCM_FIU_UMA_CMD_DUM2 … #define NPCM_FIU_UMA_CMD_DUM1 … #define NPCM_FIU_UMA_CMD_CMD … /* FIU UMA Address Register */ #define NPCM_FIU_UMA_ADDR_UMA_ADDR … #define NPCM_FIU_UMA_ADDR_AB3 … #define NPCM_FIU_UMA_ADDR_AB2 … #define NPCM_FIU_UMA_ADDR_AB1 … #define NPCM_FIU_UMA_ADDR_AB0 … /* FIU UMA Write Data Bytes 0-3 Register */ #define NPCM_FIU_UMA_DW0_WB3 … #define NPCM_FIU_UMA_DW0_WB2 … #define NPCM_FIU_UMA_DW0_WB1 … #define NPCM_FIU_UMA_DW0_WB0 … /* FIU UMA Write Data Bytes 4-7 Register */ #define NPCM_FIU_UMA_DW1_WB7 … #define NPCM_FIU_UMA_DW1_WB6 … #define NPCM_FIU_UMA_DW1_WB5 … #define NPCM_FIU_UMA_DW1_WB4 … /* FIU UMA Write Data Bytes 8-11 Register */ #define NPCM_FIU_UMA_DW2_WB11 … #define NPCM_FIU_UMA_DW2_WB10 … #define NPCM_FIU_UMA_DW2_WB9 … #define NPCM_FIU_UMA_DW2_WB8 … /* FIU UMA Write Data Bytes 12-15 Register */ #define NPCM_FIU_UMA_DW3_WB15 … #define NPCM_FIU_UMA_DW3_WB14 … #define NPCM_FIU_UMA_DW3_WB13 … #define NPCM_FIU_UMA_DW3_WB12 … /* FIU UMA Read Data Bytes 0-3 Register */ #define NPCM_FIU_UMA_DR0_RB3 … #define NPCM_FIU_UMA_DR0_RB2 … #define NPCM_FIU_UMA_DR0_RB1 … #define NPCM_FIU_UMA_DR0_RB0 … /* FIU UMA Read Data Bytes 4-7 Register */ #define NPCM_FIU_UMA_DR1_RB15 … #define NPCM_FIU_UMA_DR1_RB14 … #define NPCM_FIU_UMA_DR1_RB13 … #define NPCM_FIU_UMA_DR1_RB12 … /* FIU UMA Read Data Bytes 8-11 Register */ #define NPCM_FIU_UMA_DR2_RB15 … #define NPCM_FIU_UMA_DR2_RB14 … #define NPCM_FIU_UMA_DR2_RB13 … #define NPCM_FIU_UMA_DR2_RB12 … /* FIU UMA Read Data Bytes 12-15 Register */ #define NPCM_FIU_UMA_DR3_RB15 … #define NPCM_FIU_UMA_DR3_RB14 … #define NPCM_FIU_UMA_DR3_RB13 … #define NPCM_FIU_UMA_DR3_RB12 … /* FIU Configuration Register */ #define NPCM_FIU_CFG_FIU_FIX … /* FIU Read Mode */ enum { … }; enum { … }; enum { … }; #define NPCM_FIU_DRD_16_BYTE_BURST … #define NPCM_FIU_DWR_16_BYTE_BURST … #define MAP_SIZE_128MB … #define MAP_SIZE_16MB … #define MAP_SIZE_8MB … #define FIU_DRD_MAX_DUMMY_NUMBER … #define NPCM_MAX_CHIP_NUM … #define CHUNK_SIZE … #define UMA_MICRO_SEC_TIMEOUT … enum { … }; struct npcm_fiu_info { … }; struct fiu_data { … }; static const struct npcm_fiu_info npcm7xx_fiu_info[] = …; static const struct fiu_data npcm7xx_fiu_data = …; static const struct npcm_fiu_info npxm8xx_fiu_info[] = …; static const struct fiu_data npxm8xx_fiu_data = …; struct npcm_fiu_spi; struct npcm_fiu_chip { … }; struct npcm_fiu_spi { … }; static const struct regmap_config npcm_mtd_regmap_config = …; static void npcm_fiu_set_drd(struct npcm_fiu_spi *fiu, const struct spi_mem_op *op) { … } static ssize_t npcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf) { … } static ssize_t npcm_fiu_direct_write(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, const void *buf) { … } static int npcm_fiu_uma_read(struct spi_mem *mem, const struct spi_mem_op *op, u32 addr, bool is_address_size, u8 *data, u32 data_size) { … } static int npcm_fiu_uma_write(struct spi_mem *mem, const struct spi_mem_op *op, u8 cmd, bool is_address_size, u8 *data, u32 data_size) { … } static int npcm_fiu_manualwrite(struct spi_mem *mem, const struct spi_mem_op *op) { … } static int npcm_fiu_read(struct spi_mem *mem, const struct spi_mem_op *op) { … } static void npcm_fiux_set_direct_wr(struct npcm_fiu_spi *fiu) { … } static void npcm_fiux_set_direct_rd(struct npcm_fiu_spi *fiu) { … } static int npcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc) { … } static int npcm_fiu_setup(struct spi_device *spi) { … } static const struct spi_controller_mem_ops npcm_fiu_mem_ops = …; static const struct of_device_id npcm_fiu_dt_ids[] = …; static int npcm_fiu_probe(struct platform_device *pdev) { … } static void npcm_fiu_remove(struct platform_device *pdev) { … } MODULE_DEVICE_TABLE(of, npcm_fiu_dt_ids); static struct platform_driver npcm_fiu_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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