linux/drivers/spi/spi-mxic.c

// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2018 Macronix International Co., Ltd.
//
// Authors:
//	Mason Yang <[email protected]>
//	zhengxunli <[email protected]>
//	Boris Brezillon <[email protected]>
//

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand-ecc-mxic.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>

#define HC_CFG
#define HC_CFG_IF_CFG(x)
#define HC_CFG_DUAL_SLAVE
#define HC_CFG_INDIVIDUAL
#define HC_CFG_NIO(x)
#define HC_CFG_TYPE(s, t)
#define HC_CFG_TYPE_SPI_NOR
#define HC_CFG_TYPE_SPI_NAND
#define HC_CFG_TYPE_SPI_RAM
#define HC_CFG_TYPE_RAW_NAND
#define HC_CFG_SLV_ACT(x)
#define HC_CFG_CLK_PH_EN
#define HC_CFG_CLK_POL_INV
#define HC_CFG_BIG_ENDIAN
#define HC_CFG_DATA_PASS
#define HC_CFG_IDLE_SIO_LVL(x)
#define HC_CFG_MAN_START_EN
#define HC_CFG_MAN_START
#define HC_CFG_MAN_CS_EN
#define HC_CFG_MAN_CS_ASSERT

#define INT_STS
#define INT_STS_EN
#define INT_SIG_EN
#define INT_STS_ALL
#define INT_RDY_PIN
#define INT_RDY_SR
#define INT_LNR_SUSP
#define INT_ECC_ERR
#define INT_CRC_ERR
#define INT_LWR_DIS
#define INT_LRD_DIS
#define INT_SDMA_INT
#define INT_DMA_FINISH
#define INT_RX_NOT_FULL
#define INT_RX_NOT_EMPTY
#define INT_TX_NOT_FULL
#define INT_TX_EMPTY

#define HC_EN
#define HC_EN_BIT

#define TXD(x)
#define RXD

#define SS_CTRL(s)
#define LRD_CFG
#define LWR_CFG
#define RWW_CFG
#define OP_READ
#define OP_DUMMY_CYC(x)
#define OP_ADDR_BYTES(x)
#define OP_CMD_BYTES(x)
#define OP_OCTA_CRC_EN
#define OP_DQS_EN
#define OP_ENHC_EN
#define OP_PREAMBLE_EN
#define OP_DATA_DDR
#define OP_DATA_BUSW(x)
#define OP_ADDR_DDR
#define OP_ADDR_BUSW(x)
#define OP_CMD_DDR
#define OP_CMD_BUSW(x)
#define OP_BUSW_1
#define OP_BUSW_2
#define OP_BUSW_4
#define OP_BUSW_8

#define OCTA_CRC
#define OCTA_CRC_IN_EN(s)
#define OCTA_CRC_CHUNK(s, x)
#define OCTA_CRC_OUT_EN(s)

#define ONFI_DIN_CNT(s)

#define LRD_CTRL
#define RWW_CTRL
#define LWR_CTRL
#define LMODE_EN
#define LMODE_SLV_ACT(x)
#define LMODE_CMD1(x)
#define LMODE_CMD0(x)

#define LRD_ADDR
#define LWR_ADDR
#define LRD_RANGE
#define LWR_RANGE

#define AXI_SLV_ADDR

#define DMAC_RD_CFG
#define DMAC_WR_CFG
#define DMAC_CFG_PERIPH_EN
#define DMAC_CFG_ALLFLUSH_EN
#define DMAC_CFG_LASTFLUSH_EN
#define DMAC_CFG_QE(x)
#define DMAC_CFG_BURST_LEN(x)
#define DMAC_CFG_BURST_SZ(x)
#define DMAC_CFG_DIR_READ
#define DMAC_CFG_START

#define DMAC_RD_CNT
#define DMAC_WR_CNT

#define SDMA_ADDR

#define DMAM_CFG
#define DMAM_CFG_START
#define DMAM_CFG_CONT
#define DMAM_CFG_SDMA_GAP(x)
#define DMAM_CFG_DIR_READ
#define DMAM_CFG_EN

#define DMAM_CNT

#define LNR_TIMER_TH

#define RDM_CFG0
#define RDM_CFG0_POLY(x)

#define RDM_CFG1
#define RDM_CFG1_RDM_EN
#define RDM_CFG1_SEED(x)

#define LWR_SUSP_CTRL
#define LWR_SUSP_CTRL_EN

#define DMAS_CTRL
#define DMAS_CTRL_EN
#define DMAS_CTRL_DIR_READ

#define DATA_STROB
#define DATA_STROB_EDO_EN
#define DATA_STROB_INV_POL
#define DATA_STROB_DELAY_2CYC

#define IDLY_CODE(x)
#define IDLY_CODE_VAL(x, v)

#define GPIO
#define GPIO_PT(x)
#define GPIO_RESET(x)
#define GPIO_HOLDB(x)
#define GPIO_WPB(x)

#define HC_VER

#define HW_TEST(x)

struct mxic_spi {};

static int mxic_spi_clk_enable(struct mxic_spi *mxic)
{}

static void mxic_spi_clk_disable(struct mxic_spi *mxic)
{}

static void mxic_spi_set_input_delay_dqs(struct mxic_spi *mxic, u8 idly_code)
{}

static int mxic_spi_clk_setup(struct mxic_spi *mxic, unsigned long freq)
{}

static int mxic_spi_set_freq(struct mxic_spi *mxic, unsigned long freq)
{}

static void mxic_spi_hw_init(struct mxic_spi *mxic)
{}

static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags)
{}

static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op,
				    unsigned int data_len)
{}

static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
			      void *rxbuf, unsigned int len)
{}

static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
					u64 offs, size_t len, void *buf)
{}

static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
					 u64 offs, size_t len,
					 const void *buf)
{}

static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
				     const struct spi_mem_op *op)
{}

static int mxic_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc)
{}

static int mxic_spi_mem_exec_op(struct spi_mem *mem,
				const struct spi_mem_op *op)
{}

static const struct spi_controller_mem_ops mxic_spi_mem_ops =;

static const struct spi_controller_mem_caps mxic_spi_mem_caps =;

static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)
{}

static int mxic_spi_transfer_one(struct spi_controller *host,
				 struct spi_device *spi,
				 struct spi_transfer *t)
{}

/* ECC wrapper */
static int mxic_spi_mem_ecc_init_ctx(struct nand_device *nand)
{}

static void mxic_spi_mem_ecc_cleanup_ctx(struct nand_device *nand)
{}

static int mxic_spi_mem_ecc_prepare_io_req(struct nand_device *nand,
					   struct nand_page_io_req *req)
{}

static int mxic_spi_mem_ecc_finish_io_req(struct nand_device *nand,
					  struct nand_page_io_req *req)
{}

static struct nand_ecc_engine_ops mxic_spi_mem_ecc_engine_pipelined_ops =;

static void mxic_spi_mem_ecc_remove(struct mxic_spi *mxic)
{}

static int mxic_spi_mem_ecc_probe(struct platform_device *pdev,
				  struct mxic_spi *mxic)
{}

static int __maybe_unused mxic_spi_runtime_suspend(struct device *dev)
{}

static int __maybe_unused mxic_spi_runtime_resume(struct device *dev)
{}

static const struct dev_pm_ops mxic_spi_dev_pm_ops =;

static int mxic_spi_probe(struct platform_device *pdev)
{}

static void mxic_spi_remove(struct platform_device *pdev)
{}

static const struct of_device_id mxic_spi_of_ids[] =;
MODULE_DEVICE_TABLE(of, mxic_spi_of_ids);

static struct platform_driver mxic_spi_driver =;
module_platform_driver();

MODULE_AUTHOR();
MODULE_DESCRIPTION();
MODULE_LICENSE();