// SPDX-License-Identifier: GPL-2.0 // PCI1xxxx SPI driver // Copyright (C) 2022 Microchip Technology Inc. // Authors: Tharun Kumar P <[email protected]> // Kumaravel Thiagarajan <[email protected]> #include <linux/bitfield.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/iopoll.h> #include <linux/irq.h> #include <linux/module.h> #include <linux/msi.h> #include <linux/pci_regs.h> #include <linux/pci.h> #include <linux/spinlock.h> #include <linux/spi/spi.h> #include "internals.h" #define DRV_NAME … #define SYS_FREQ_DEFAULT … #define PCI1XXXX_SPI_MAX_CLOCK_HZ … #define PCI1XXXX_SPI_CLK_20MHZ … #define PCI1XXXX_SPI_CLK_15MHZ … #define PCI1XXXX_SPI_CLK_12MHZ … #define PCI1XXXX_SPI_CLK_10MHZ … #define PCI1XXXX_SPI_MIN_CLOCK_HZ … #define PCI1XXXX_SPI_BUFFER_SIZE … #define SPI_MST_CTL_DEVSEL_MASK … #define SPI_MST_CTL_CMD_LEN_MASK … #define SPI_MST_CTL_SPEED_MASK … #define SPI_MSI_VECTOR_SEL_MASK … #define SPI_MST_CTL_FORCE_CE … #define SPI_MST_CTL_MODE_SEL … #define SPI_MST_CTL_GO … #define SPI_PERI_ADDR_BASE … #define SPI_SYSTEM_ADDR_BASE … #define SPI_MST1_ADDR_BASE … #define DEV_REV_REG … #define SPI_SYSLOCK_REG … #define SPI_CONFIG_PERI_ENABLE_REG … #define SPI_PERI_ENBLE_PF_MASK … #define DEV_REV_MASK … #define SPI_SYSLOCK … #define SPI0 … #define SPI1 … /* DMA Related Registers */ #define SPI_DMA_ADDR_BASE … #define SPI_DMA_GLOBAL_WR_ENGINE_EN … #define SPI_DMA_WR_DOORBELL_REG … #define SPI_DMA_GLOBAL_RD_ENGINE_EN … #define SPI_DMA_RD_DOORBELL_REG … #define SPI_DMA_INTR_WR_STS … #define SPI_DMA_WR_INT_MASK … #define SPI_DMA_INTR_WR_CLR … #define SPI_DMA_ERR_WR_STS … #define SPI_DMA_INTR_IMWR_WDONE_LOW … #define SPI_DMA_INTR_IMWR_WDONE_HIGH … #define SPI_DMA_INTR_IMWR_WABORT_LOW … #define SPI_DMA_INTR_IMWR_WABORT_HIGH … #define SPI_DMA_INTR_WR_IMWR_DATA … #define SPI_DMA_INTR_RD_STS … #define SPI_DMA_RD_INT_MASK … #define SPI_DMA_INTR_RD_CLR … #define SPI_DMA_ERR_RD_STS … #define SPI_DMA_INTR_IMWR_RDONE_LOW … #define SPI_DMA_INTR_IMWR_RDONE_HIGH … #define SPI_DMA_INTR_IMWR_RABORT_LOW … #define SPI_DMA_INTR_IMWR_RABORT_HIGH … #define SPI_DMA_INTR_RD_IMWR_DATA … #define SPI_DMA_CH0_WR_BASE … #define SPI_DMA_CH0_RD_BASE … #define SPI_DMA_CH1_WR_BASE … #define SPI_DMA_CH1_RD_BASE … #define SPI_DMA_CH_CTL1_OFFSET … #define SPI_DMA_CH_XFER_LEN_OFFSET … #define SPI_DMA_CH_SAR_LO_OFFSET … #define SPI_DMA_CH_SAR_HI_OFFSET … #define SPI_DMA_CH_DAR_LO_OFFSET … #define SPI_DMA_CH_DAR_HI_OFFSET … #define SPI_DMA_CH0_DONE_INT … #define SPI_DMA_CH1_DONE_INT … #define SPI_DMA_CH0_ABORT_INT … #define SPI_DMA_CH1_ABORT_INT … #define SPI_DMA_DONE_INT_MASK … #define SPI_DMA_ABORT_INT_MASK … #define DMA_CH_CONTROL_LIE … #define DMA_CH_CONTROL_RIE … #define DMA_INTR_EN … /* x refers to SPI Host Controller HW instance id in the below macros - 0 or 1 */ #define SPI_MST_CMD_BUF_OFFSET(x) … #define SPI_MST_RSP_BUF_OFFSET(x) … #define SPI_MST_CTL_REG_OFFSET(x) … #define SPI_MST_EVENT_REG_OFFSET(x) … #define SPI_MST_EVENT_MASK_REG_OFFSET(x) … #define SPI_MST_PAD_CTL_REG_OFFSET(x) … #define SPIALERT_MST_DB_REG_OFFSET(x) … #define SPIALERT_MST_VAL_REG_OFFSET(x) … #define SPI_PCI_CTRL_REG_OFFSET(x) … #define PCI1XXXX_IRQ_FLAGS … #define SPI_MAX_DATA_LEN … #define PCI1XXXX_SPI_TIMEOUT … #define SYSLOCK_RETRY_CNT … #define SPI_DMA_ENGINE_EN … #define SPI_DMA_ENGINE_DIS … #define SPI_INTR … #define SPI_FORCE_CE … #define SPI_CHIP_SEL_COUNT … #define VENDOR_ID_MCHP … #define SPI_SUSPEND_CONFIG … #define SPI_RESUME_CONFIG … struct pci1xxxx_spi_internal { … }; struct pci1xxxx_spi { … }; static const struct pci_device_id pci1xxxx_spi_pci_id_table[] = …; MODULE_DEVICE_TABLE(pci, pci1xxxx_spi_pci_id_table); static int pci1xxxx_set_sys_lock(struct pci1xxxx_spi *par) { … } static int pci1xxxx_acquire_sys_lock(struct pci1xxxx_spi *par) { … } static void pci1xxxx_release_sys_lock(struct pci1xxxx_spi *par) { … } static int pci1xxxx_check_spi_can_dma(struct pci1xxxx_spi *spi_bus, int irq) { … } static int pci1xxxx_spi_dma_init(struct pci1xxxx_spi *spi_bus, int irq) { … } static void pci1xxxx_spi_set_cs(struct spi_device *spi, bool enable) { … } static u8 pci1xxxx_get_clock_div(u32 hz) { … } static void pci1xxxx_spi_setup_dma_to_io(struct pci1xxxx_spi_internal *p, dma_addr_t dma_addr, u32 len) { … } static void pci1xxxx_spi_setup_dma_from_io(struct pci1xxxx_spi_internal *p, dma_addr_t dma_addr, u32 len) { … } static void pci1xxxx_spi_setup(struct pci1xxxx_spi *par, u8 hw_inst, u32 mode, u8 clkdiv, u32 len) { … } static void pci1xxxx_start_spi_xfer(struct pci1xxxx_spi_internal *p, u8 hw_inst) { … } static int pci1xxxx_spi_transfer_with_io(struct spi_controller *spi_ctlr, struct spi_device *spi, struct spi_transfer *xfer) { … } static int pci1xxxx_spi_transfer_with_dma(struct spi_controller *spi_ctlr, struct spi_device *spi, struct spi_transfer *xfer) { … } static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr, struct spi_device *spi, struct spi_transfer *xfer) { … } static irqreturn_t pci1xxxx_spi_isr_io(int irq, void *dev) { … } static void pci1xxxx_spi_setup_next_dma_transfer(struct pci1xxxx_spi_internal *p) { … } static irqreturn_t pci1xxxx_spi_isr_dma(int irq, void *dev) { … } static irqreturn_t pci1xxxx_spi_isr(int irq, void *dev) { … } static bool pci1xxxx_spi_can_dma(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *xfer) { … } static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { … } static void store_restore_config(struct pci1xxxx_spi *spi_ptr, struct pci1xxxx_spi_internal *spi_sub_ptr, u8 inst, bool store) { … } static int pci1xxxx_spi_resume(struct device *dev) { … } static int pci1xxxx_spi_suspend(struct device *dev) { … } static DEFINE_SIMPLE_DEV_PM_OPS(spi_pm_ops, pci1xxxx_spi_suspend, pci1xxxx_spi_resume); static struct pci_driver pci1xxxx_spi_driver = …; module_pci_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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