linux/drivers/spi/spi-pxa2xx.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
 * Copyright (C) 2013, 2021 Intel Corporation
 */

#include <linux/atomic.h>
#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dmaengine.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/math64.h>
#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/types.h>

#include <linux/spi/spi.h>

#include "internals.h"
#include "spi-pxa2xx.h"

#define TIMOUT_DFLT

/*
 * For testing SSCR1 changes that require SSP restart, basically
 * everything except the service and interrupt enables, the PXA270 developer
 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
 * list, but the PXA255 developer manual says all bits without really meaning
 * the service and interrupt enables.
 */
#define SSCR1_CHANGE_MASK

#define QUARK_X1000_SSCR1_CHANGE_MASK

#define CE4100_SSCR1_CHANGE_MASK

struct chip_data {};

#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE
#define LPSS_CS_CONTROL_SW_MODE
#define LPSS_CS_CONTROL_CS_HIGH
#define LPSS_CAPS_CS_EN_SHIFT
#define LPSS_CAPS_CS_EN_MASK

#define LPSS_PRIV_CLOCK_GATE
#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK
#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON

struct lpss_config {};

/* Keep these sorted with enum pxa_ssp_type */
static const struct lpss_config lpss_platforms[] =;

static inline const struct lpss_config
*lpss_get_config(const struct driver_data *drv_data)
{}

static bool is_lpss_ssp(const struct driver_data *drv_data)
{}

static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
{}

static bool is_mmp2_ssp(const struct driver_data *drv_data)
{}

static bool is_mrfld_ssp(const struct driver_data *drv_data)
{}

static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value)
{}

static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
{}

static u32
pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
{}

static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
{}

static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
				     u32 *sccr1_reg)
{}

static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
				   u32 *sccr1_reg, u32 threshold)
{}

static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
				  u32 clk_div, u8 bits)
{}

/*
 * Read and write LPSS SSP private registers. Caller must first check that
 * is_lpss_ssp() returns true before these can be called.
 */
static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
{}

static void __lpss_ssp_write_priv(struct driver_data *drv_data,
				  unsigned offset, u32 value)
{}

/*
 * lpss_ssp_setup - perform LPSS SSP specific setup
 * @drv_data: pointer to the driver private data
 *
 * Perform LPSS SSP specific setup. This function must be called first if
 * one is going to use LPSS SSP private registers.
 */
static void lpss_ssp_setup(struct driver_data *drv_data)
{}

static void lpss_ssp_select_cs(struct spi_device *spi,
			       const struct lpss_config *config)
{}

static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
{}

static void cs_assert(struct spi_device *spi)
{}

static void cs_deassert(struct spi_device *spi)
{}

static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
{}

int pxa2xx_spi_flush(struct driver_data *drv_data)
{}

static void pxa2xx_spi_off(struct driver_data *drv_data)
{}

static int null_writer(struct driver_data *drv_data)
{}

static int null_reader(struct driver_data *drv_data)
{}

static int u8_writer(struct driver_data *drv_data)
{}

static int u8_reader(struct driver_data *drv_data)
{}

static int u16_writer(struct driver_data *drv_data)
{}

static int u16_reader(struct driver_data *drv_data)
{}

static int u32_writer(struct driver_data *drv_data)
{}

static int u32_reader(struct driver_data *drv_data)
{}

static void reset_sccr1(struct driver_data *drv_data)
{}

static void int_stop_and_reset(struct driver_data *drv_data)
{}

static void int_error_stop(struct driver_data *drv_data, const char *msg, int err)
{}

static void int_transfer_complete(struct driver_data *drv_data)
{}

static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
{}

static void handle_bad_msg(struct driver_data *drv_data)
{}

static irqreturn_t ssp_int(int irq, void *dev_id)
{}

/*
 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
 * input frequency by fractions of 2^24. It also has a divider by 5.
 *
 * There are formulas to get baud rate value for given input frequency and
 * divider parameters, such as DDS_CLK_RATE and SCR:
 *
 * Fsys = 200MHz
 *
 * Fssp = Fsys * DDS_CLK_RATE / 2^24			(1)
 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1))		(2)
 *
 * DDS_CLK_RATE either 2^n or 2^n / 5.
 * SCR is in range 0 .. 255
 *
 * Divisor = 5^i * 2^j * 2 * k
 *       i = [0, 1]      i = 1 iff j = 0 or j > 3
 *       j = [0, 23]     j = 0 iff i = 1
 *       k = [1, 256]
 * Special case: j = 0, i = 1: Divisor = 2 / 5
 *
 * Accordingly to the specification the recommended values for DDS_CLK_RATE
 * are:
 *	Case 1:		2^n, n = [0, 23]
 *	Case 2:		2^24 * 2 / 5 (0x666666)
 *	Case 3:		less than or equal to 2^24 / 5 / 16 (0x33333)
 *
 * In all cases the lowest possible value is better.
 *
 * The function calculates parameters for all cases and chooses the one closest
 * to the asked baud rate.
 */
static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
{}

static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
{}

static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
					   int rate)
{}

static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
			       struct spi_device *spi,
			       struct spi_transfer *xfer)
{}

static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
				   struct spi_device *spi,
				   struct spi_transfer *transfer)
{}

static int pxa2xx_spi_target_abort(struct spi_controller *controller)
{}

static void pxa2xx_spi_handle_err(struct spi_controller *controller,
				 struct spi_message *msg)
{}

static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
{}

static int setup(struct spi_device *spi)
{}

static void cleanup(struct spi_device *spi)
{}

static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
				      unsigned int cs)
{}

static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
{}

int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp)
{}
EXPORT_SYMBOL_NS_GPL();

void pxa2xx_spi_remove(struct device *dev)
{}
EXPORT_SYMBOL_NS_GPL();

static int pxa2xx_spi_suspend(struct device *dev)
{}

static int pxa2xx_spi_resume(struct device *dev)
{}

static int pxa2xx_spi_runtime_suspend(struct device *dev)
{}

static int pxa2xx_spi_runtime_resume(struct device *dev)
{}

EXPORT_NS_GPL_DEV_PM_OPS(pxa2xx_spi_pm_ops, SPI_PXA2xx) =;

MODULE_AUTHOR();
MODULE_DESCRIPTION();
MODULE_LICENSE();