// SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. #include <linux/clk.h> #include <linux/dmapool.h> #include <linux/dma-mapping.h> #include <linux/interconnect.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pinctrl/consumer.h> #include <linux/pm_runtime.h> #include <linux/pm_opp.h> #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> #define QSPI_NUM_CS … #define QSPI_BYTES_PER_WORD … #define MSTR_CONFIG … #define FULL_CYCLE_MODE … #define FB_CLK_EN … #define PIN_HOLDN … #define PIN_WPN … #define DMA_ENABLE … #define BIG_ENDIAN_MODE … #define SPI_MODE_MSK … #define SPI_MODE_SHFT … #define CHIP_SELECT_NUM … #define SBL_EN … #define LPA_BASE_MSK … #define LPA_BASE_SHFT … #define TX_DATA_DELAY_MSK … #define TX_DATA_DELAY_SHFT … #define TX_CLK_DELAY_MSK … #define TX_CLK_DELAY_SHFT … #define TX_CS_N_DELAY_MSK … #define TX_CS_N_DELAY_SHFT … #define TX_DATA_OE_DELAY_MSK … #define TX_DATA_OE_DELAY_SHFT … #define AHB_MASTER_CFG … #define HMEM_TYPE_START_MID_TRANS_MSK … #define HMEM_TYPE_START_MID_TRANS_SHFT … #define HMEM_TYPE_LAST_TRANS_MSK … #define HMEM_TYPE_LAST_TRANS_SHFT … #define USE_HMEMTYPE_LAST_ON_DESC_OR_CHAIN_MSK … #define USE_HMEMTYPE_LAST_ON_DESC_OR_CHAIN_SHFT … #define HMEMTYPE_READ_TRANS_MSK … #define HMEMTYPE_READ_TRANS_SHFT … #define HSHARED … #define HINNERSHARED … #define MSTR_INT_EN … #define MSTR_INT_STATUS … #define RESP_FIFO_UNDERRUN … #define RESP_FIFO_NOT_EMPTY … #define RESP_FIFO_RDY … #define HRESP_FROM_NOC_ERR … #define WR_FIFO_EMPTY … #define WR_FIFO_FULL … #define WR_FIFO_OVERRUN … #define TRANSACTION_DONE … #define DMA_CHAIN_DONE … #define QSPI_ERR_IRQS … #define QSPI_ALL_IRQS … #define PIO_XFER_CTRL … #define REQUEST_COUNT_MSK … #define PIO_XFER_CFG … #define TRANSFER_DIRECTION … #define MULTI_IO_MODE_MSK … #define MULTI_IO_MODE_SHFT … #define TRANSFER_FRAGMENT … #define SDR_1BIT … #define SDR_2BIT … #define SDR_4BIT … #define DDR_1BIT … #define DDR_2BIT … #define DDR_4BIT … #define DMA_DESC_SINGLE_SPI … #define DMA_DESC_DUAL_SPI … #define DMA_DESC_QUAD_SPI … #define PIO_XFER_STATUS … #define WR_FIFO_BYTES_MSK … #define WR_FIFO_BYTES_SHFT … #define PIO_DATAOUT_1B … #define PIO_DATAOUT_4B … #define RD_FIFO_CFG … #define CONTINUOUS_MODE … #define RD_FIFO_STATUS … #define FIFO_EMPTY … #define WR_CNTS_MSK … #define WR_CNTS_SHFT … #define RDY_64BYTE … #define RDY_32BYTE … #define RDY_16BYTE … #define FIFO_RDY … #define RD_FIFO_RESET … #define RESET_FIFO … #define NEXT_DMA_DESC_ADDR … #define CURRENT_DMA_DESC_ADDR … #define CURRENT_MEM_ADDR … #define CUR_MEM_ADDR … #define HW_VERSION … #define RD_FIFO … #define SAMPLING_CLK_CFG … #define SAMPLING_CLK_STATUS … #define QSPI_ALIGN_REQ … enum qspi_dir { … }; struct qspi_cmd_desc { … }; struct qspi_xfer { … }; enum qspi_clocks { … }; /* * Number of entries in sgt returned from spi framework that- * will be supported. Can be modified as required. * In practice, given max_dma_len is 64KB, the number of * entries is not expected to exceed 1. */ #define QSPI_MAX_SG … struct qcom_qspi { … }; static u32 qspi_buswidth_to_iomode(struct qcom_qspi *ctrl, unsigned int buswidth) { … } static void qcom_qspi_pio_xfer_cfg(struct qcom_qspi *ctrl) { … } static void qcom_qspi_pio_xfer_ctrl(struct qcom_qspi *ctrl) { … } static void qcom_qspi_pio_xfer(struct qcom_qspi *ctrl) { … } static void qcom_qspi_handle_err(struct spi_controller *host, struct spi_message *msg) { … } static int qcom_qspi_set_speed(struct qcom_qspi *ctrl, unsigned long speed_hz) { … } static int qcom_qspi_alloc_desc(struct qcom_qspi *ctrl, dma_addr_t dma_ptr, uint32_t n_bytes) { … } static int qcom_qspi_setup_dma_desc(struct qcom_qspi *ctrl, struct spi_transfer *xfer) { … } static void qcom_qspi_dma_xfer(struct qcom_qspi *ctrl) { … } /* Switch to DMA if transfer length exceeds this */ #define QSPI_MAX_BYTES_FIFO … static bool qcom_qspi_can_dma(struct spi_controller *ctlr, struct spi_device *slv, struct spi_transfer *xfer) { … } static int qcom_qspi_transfer_one(struct spi_controller *host, struct spi_device *slv, struct spi_transfer *xfer) { … } static int qcom_qspi_prepare_message(struct spi_controller *host, struct spi_message *message) { … } static int qcom_qspi_alloc_dma(struct qcom_qspi *ctrl) { … } static irqreturn_t pio_read(struct qcom_qspi *ctrl) { … } static irqreturn_t pio_write(struct qcom_qspi *ctrl) { … } static irqreturn_t qcom_qspi_irq(int irq, void *dev_id) { … } static int qcom_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) { … } static const struct spi_controller_mem_ops qcom_qspi_mem_ops = …; static int qcom_qspi_probe(struct platform_device *pdev) { … } static void qcom_qspi_remove(struct platform_device *pdev) { … } static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev) { … } static int __maybe_unused qcom_qspi_runtime_resume(struct device *dev) { … } static int __maybe_unused qcom_qspi_suspend(struct device *dev) { … } static int __maybe_unused qcom_qspi_resume(struct device *dev) { … } static const struct dev_pm_ops qcom_qspi_dev_pm_ops = …; static const struct of_device_id qcom_qspi_dt_match[] = …; MODULE_DEVICE_TABLE(of, qcom_qspi_dt_match); static struct platform_driver qcom_qspi_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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