// SPDX-License-Identifier: GPL-2.0-only /* * Rockchip Serial Flash Controller Driver * * Copyright (c) 2017-2021, Rockchip Inc. * Author: Shawn Lin <[email protected]> * Chris Morgan <[email protected]> * Jon Lin <[email protected]> */ #include <linux/bitops.h> #include <linux/clk.h> #include <linux/completion.h> #include <linux/dma-mapping.h> #include <linux/iopoll.h> #include <linux/mm.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/interrupt.h> #include <linux/spi/spi-mem.h> /* System control */ #define SFC_CTRL … #define SFC_CTRL_PHASE_SEL_NEGETIVE … #define SFC_CTRL_CMD_BITS_SHIFT … #define SFC_CTRL_ADDR_BITS_SHIFT … #define SFC_CTRL_DATA_BITS_SHIFT … /* Interrupt mask */ #define SFC_IMR … #define SFC_IMR_RX_FULL … #define SFC_IMR_RX_UFLOW … #define SFC_IMR_TX_OFLOW … #define SFC_IMR_TX_EMPTY … #define SFC_IMR_TRAN_FINISH … #define SFC_IMR_BUS_ERR … #define SFC_IMR_NSPI_ERR … #define SFC_IMR_DMA … /* Interrupt clear */ #define SFC_ICLR … #define SFC_ICLR_RX_FULL … #define SFC_ICLR_RX_UFLOW … #define SFC_ICLR_TX_OFLOW … #define SFC_ICLR_TX_EMPTY … #define SFC_ICLR_TRAN_FINISH … #define SFC_ICLR_BUS_ERR … #define SFC_ICLR_NSPI_ERR … #define SFC_ICLR_DMA … /* FIFO threshold level */ #define SFC_FTLR … #define SFC_FTLR_TX_SHIFT … #define SFC_FTLR_TX_MASK … #define SFC_FTLR_RX_SHIFT … #define SFC_FTLR_RX_MASK … /* Reset FSM and FIFO */ #define SFC_RCVR … #define SFC_RCVR_RESET … /* Enhanced mode */ #define SFC_AX … /* Address Bit number */ #define SFC_ABIT … /* Interrupt status */ #define SFC_ISR … #define SFC_ISR_RX_FULL_SHIFT … #define SFC_ISR_RX_UFLOW_SHIFT … #define SFC_ISR_TX_OFLOW_SHIFT … #define SFC_ISR_TX_EMPTY_SHIFT … #define SFC_ISR_TX_FINISH_SHIFT … #define SFC_ISR_BUS_ERR_SHIFT … #define SFC_ISR_NSPI_ERR_SHIFT … #define SFC_ISR_DMA_SHIFT … /* FIFO status */ #define SFC_FSR … #define SFC_FSR_TX_IS_FULL … #define SFC_FSR_TX_IS_EMPTY … #define SFC_FSR_RX_IS_EMPTY … #define SFC_FSR_RX_IS_FULL … #define SFC_FSR_TXLV_MASK … #define SFC_FSR_TXLV_SHIFT … #define SFC_FSR_RXLV_MASK … #define SFC_FSR_RXLV_SHIFT … /* FSM status */ #define SFC_SR … #define SFC_SR_IS_IDLE … #define SFC_SR_IS_BUSY … /* Raw interrupt status */ #define SFC_RISR … #define SFC_RISR_RX_FULL … #define SFC_RISR_RX_UNDERFLOW … #define SFC_RISR_TX_OVERFLOW … #define SFC_RISR_TX_EMPTY … #define SFC_RISR_TRAN_FINISH … #define SFC_RISR_BUS_ERR … #define SFC_RISR_NSPI_ERR … #define SFC_RISR_DMA … /* Version */ #define SFC_VER … #define SFC_VER_3 … #define SFC_VER_4 … #define SFC_VER_5 … /* Delay line controller resiter */ #define SFC_DLL_CTRL0 … #define SFC_DLL_CTRL0_SCLK_SMP_DLL … #define SFC_DLL_CTRL0_DLL_MAX_VER4 … #define SFC_DLL_CTRL0_DLL_MAX_VER5 … /* Master trigger */ #define SFC_DMA_TRIGGER … #define SFC_DMA_TRIGGER_START … /* Src or Dst addr for master */ #define SFC_DMA_ADDR … /* Length control register extension 32GB */ #define SFC_LEN_CTRL … #define SFC_LEN_CTRL_TRB_SEL … #define SFC_LEN_EXT … /* Command */ #define SFC_CMD … #define SFC_CMD_IDX_SHIFT … #define SFC_CMD_DUMMY_SHIFT … #define SFC_CMD_DIR_SHIFT … #define SFC_CMD_DIR_RD … #define SFC_CMD_DIR_WR … #define SFC_CMD_ADDR_SHIFT … #define SFC_CMD_ADDR_0BITS … #define SFC_CMD_ADDR_24BITS … #define SFC_CMD_ADDR_32BITS … #define SFC_CMD_ADDR_XBITS … #define SFC_CMD_TRAN_BYTES_SHIFT … #define SFC_CMD_CS_SHIFT … /* Address */ #define SFC_ADDR … /* Data */ #define SFC_DATA … /* The controller and documentation reports that it supports up to 4 CS * devices (0-3), however I have only been able to test a single CS (CS 0) * due to the configuration of my device. */ #define SFC_MAX_CHIPSELECT_NUM … /* The SFC can transfer max 16KB - 1 at one time * we set it to 15.5KB here for alignment. */ #define SFC_MAX_IOSIZE_VER3 … /* DMA is only enabled for large data transmission */ #define SFC_DMA_TRANS_THRETHOLD … /* Maximum clock values from datasheet suggest keeping clock value under * 150MHz. No minimum or average value is suggested. */ #define SFC_MAX_SPEED … struct rockchip_sfc { … }; static int rockchip_sfc_reset(struct rockchip_sfc *sfc) { … } static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) { … } static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) { … } static void rockchip_sfc_irq_unmask(struct rockchip_sfc *sfc, u32 mask) { … } static void rockchip_sfc_irq_mask(struct rockchip_sfc *sfc, u32 mask) { … } static int rockchip_sfc_init(struct rockchip_sfc *sfc) { … } static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) { … } static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) { … } static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) { … } static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, struct spi_mem *mem, const struct spi_mem_op *op, u32 len) { … } static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) { … } static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) { … } static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) { … } static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, const struct spi_mem_op *op, u32 len) { … } static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, const struct spi_mem_op *op, u32 len) { … } static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) { … } static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static int rockchip_sfc_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) { … } static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = …; static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id) { … } static int rockchip_sfc_probe(struct platform_device *pdev) { … } static void rockchip_sfc_remove(struct platform_device *pdev) { … } static const struct of_device_id rockchip_sfc_dt_ids[] = …; MODULE_DEVICE_TABLE(of, rockchip_sfc_dt_ids); static struct platform_driver rockchip_sfc_driver = …; module_platform_driver(…) …; MODULE_LICENSE(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …;
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