// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd * Author: Addy Ke <[email protected]> */ #include <linux/clk.h> #include <linux/dmaengine.h> #include <linux/interrupt.h> #include <linux/module.h> #include <linux/of.h> #include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> #include <linux/spi/spi.h> #include <linux/pm_runtime.h> #include <linux/scatterlist.h> #define DRIVER_NAME … #define ROCKCHIP_SPI_CLR_BITS(reg, bits) … #define ROCKCHIP_SPI_SET_BITS(reg, bits) … /* SPI register offsets */ #define ROCKCHIP_SPI_CTRLR0 … #define ROCKCHIP_SPI_CTRLR1 … #define ROCKCHIP_SPI_SSIENR … #define ROCKCHIP_SPI_SER … #define ROCKCHIP_SPI_BAUDR … #define ROCKCHIP_SPI_TXFTLR … #define ROCKCHIP_SPI_RXFTLR … #define ROCKCHIP_SPI_TXFLR … #define ROCKCHIP_SPI_RXFLR … #define ROCKCHIP_SPI_SR … #define ROCKCHIP_SPI_IPR … #define ROCKCHIP_SPI_IMR … #define ROCKCHIP_SPI_ISR … #define ROCKCHIP_SPI_RISR … #define ROCKCHIP_SPI_ICR … #define ROCKCHIP_SPI_DMACR … #define ROCKCHIP_SPI_DMATDLR … #define ROCKCHIP_SPI_DMARDLR … #define ROCKCHIP_SPI_VERSION … #define ROCKCHIP_SPI_TXDR … #define ROCKCHIP_SPI_RXDR … /* Bit fields in CTRLR0 */ #define CR0_DFS_OFFSET … #define CR0_DFS_4BIT … #define CR0_DFS_8BIT … #define CR0_DFS_16BIT … #define CR0_CFS_OFFSET … #define CR0_SCPH_OFFSET … #define CR0_SCPOL_OFFSET … #define CR0_CSM_OFFSET … #define CR0_CSM_KEEP … /* ss_n be high for half sclk_out cycles */ #define CR0_CSM_HALF … /* ss_n be high for one sclk_out cycle */ #define CR0_CSM_ONE … /* ss_n to sclk_out delay */ #define CR0_SSD_OFFSET … /* * The period between ss_n active and * sclk_out active is half sclk_out cycles */ #define CR0_SSD_HALF … /* * The period between ss_n active and * sclk_out active is one sclk_out cycle */ #define CR0_SSD_ONE … #define CR0_EM_OFFSET … #define CR0_EM_LITTLE … #define CR0_EM_BIG … #define CR0_FBM_OFFSET … #define CR0_FBM_MSB … #define CR0_FBM_LSB … #define CR0_BHT_OFFSET … #define CR0_BHT_16BIT … #define CR0_BHT_8BIT … #define CR0_RSD_OFFSET … #define CR0_RSD_MAX … #define CR0_FRF_OFFSET … #define CR0_FRF_SPI … #define CR0_FRF_SSP … #define CR0_FRF_MICROWIRE … #define CR0_XFM_OFFSET … #define CR0_XFM_MASK … #define CR0_XFM_TR … #define CR0_XFM_TO … #define CR0_XFM_RO … #define CR0_OPM_OFFSET … #define CR0_OPM_HOST … #define CR0_OPM_TARGET … #define CR0_SOI_OFFSET … #define CR0_MTM_OFFSET … /* Bit fields in SER, 2bit */ #define SER_MASK … /* Bit fields in BAUDR */ #define BAUDR_SCKDV_MIN … #define BAUDR_SCKDV_MAX … /* Bit fields in SR, 6bit */ #define SR_MASK … #define SR_BUSY … #define SR_TF_FULL … #define SR_TF_EMPTY … #define SR_RF_EMPTY … #define SR_RF_FULL … #define SR_TARGET_TX_BUSY … /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ #define INT_MASK … #define INT_TF_EMPTY … #define INT_TF_OVERFLOW … #define INT_RF_UNDERFLOW … #define INT_RF_OVERFLOW … #define INT_RF_FULL … #define INT_CS_INACTIVE … /* Bit fields in ICR, 4bit */ #define ICR_MASK … #define ICR_ALL … #define ICR_RF_UNDERFLOW … #define ICR_RF_OVERFLOW … #define ICR_TF_OVERFLOW … /* Bit fields in DMACR */ #define RF_DMA_EN … #define TF_DMA_EN … /* Driver state flags */ #define RXDMA … #define TXDMA … /* sclk_out: spi host internal logic in rk3x can support 50Mhz */ #define MAX_SCLK_OUT … /* * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However, * the controller seems to hang when given 0x10000, so stick with this for now. */ #define ROCKCHIP_SPI_MAX_TRANLEN … #define ROCKCHIP_SPI_MAX_NATIVE_CS_NUM … #define ROCKCHIP_SPI_VER2_TYPE1 … #define ROCKCHIP_SPI_VER2_TYPE2 … #define ROCKCHIP_AUTOSUSPEND_TIMEOUT … struct rockchip_spi { … }; static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable) { … } static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool target_mode) { … } static u32 get_fifo_len(struct rockchip_spi *rs) { … } static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) { … } static void rockchip_spi_handle_err(struct spi_controller *ctlr, struct spi_message *msg) { … } static void rockchip_spi_pio_writer(struct rockchip_spi *rs) { … } static void rockchip_spi_pio_reader(struct rockchip_spi *rs) { … } static irqreturn_t rockchip_spi_isr(int irq, void *dev_id) { … } static int rockchip_spi_prepare_irq(struct rockchip_spi *rs, struct spi_controller *ctlr, struct spi_transfer *xfer) { … } static void rockchip_spi_dma_rxcb(void *data) { … } static void rockchip_spi_dma_txcb(void *data) { … } static u32 rockchip_spi_calc_burst_size(u32 data_len) { … } static int rockchip_spi_prepare_dma(struct rockchip_spi *rs, struct spi_controller *ctlr, struct spi_transfer *xfer) { … } static int rockchip_spi_config(struct rockchip_spi *rs, struct spi_device *spi, struct spi_transfer *xfer, bool use_dma, bool target_mode) { … } static size_t rockchip_spi_max_transfer_size(struct spi_device *spi) { … } static int rockchip_spi_target_abort(struct spi_controller *ctlr) { … } static int rockchip_spi_transfer_one( struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *xfer) { … } static bool rockchip_spi_can_dma(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *xfer) { … } static int rockchip_spi_setup(struct spi_device *spi) { … } static int rockchip_spi_probe(struct platform_device *pdev) { … } static void rockchip_spi_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int rockchip_spi_suspend(struct device *dev) { … } static int rockchip_spi_resume(struct device *dev) { … } #endif /* CONFIG_PM_SLEEP */ #ifdef CONFIG_PM static int rockchip_spi_runtime_suspend(struct device *dev) { … } static int rockchip_spi_runtime_resume(struct device *dev) { … } #endif /* CONFIG_PM */ static const struct dev_pm_ops rockchip_spi_pm = …; static const struct of_device_id rockchip_spi_dt_match[] = …; MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); static struct platform_driver rockchip_spi_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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