// SPDX-License-Identifier: GPL-2.0 /* * SuperH MSIOF SPI Controller Interface * * Copyright (c) 2009 Magnus Damm * Copyright (C) 2014 Renesas Electronics Corporation * Copyright (C) 2014-2017 Glider bvba */ #include <linux/bitmap.h> #include <linux/clk.h> #include <linux/completion.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> #include <linux/err.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/sh_dma.h> #include <linux/spi/sh_msiof.h> #include <linux/spi/spi.h> #include <asm/unaligned.h> #define SH_MSIOF_FLAG_FIXED_DTDL_200 … struct sh_msiof_chipdata { … }; struct sh_msiof_spi_priv { … }; #define MAX_SS … #define SITMDR1 … #define SITMDR2 … #define SITMDR3 … #define SIRMDR1 … #define SIRMDR2 … #define SIRMDR3 … #define SITSCR … #define SIRSCR … #define SICTR … #define SIFCTR … #define SISTR … #define SIIER … #define SITDR1 … #define SITDR2 … #define SITFDR … #define SIRDR1 … #define SIRDR2 … #define SIRFDR … /* SITMDR1 and SIRMDR1 */ #define SIMDR1_TRMD … #define SIMDR1_SYNCMD_MASK … #define SIMDR1_SYNCMD_SPI … #define SIMDR1_SYNCMD_LR … #define SIMDR1_SYNCAC_SHIFT … #define SIMDR1_BITLSB_SHIFT … #define SIMDR1_DTDL_SHIFT … #define SIMDR1_SYNCDL_SHIFT … #define SIMDR1_FLD_MASK … #define SIMDR1_FLD_SHIFT … #define SIMDR1_XXSTP … /* SITMDR1 */ #define SITMDR1_PCON … #define SITMDR1_SYNCCH_MASK … #define SITMDR1_SYNCCH_SHIFT … /* SITMDR2 and SIRMDR2 */ #define SIMDR2_BITLEN1(i) … #define SIMDR2_WDLEN1(i) … #define SIMDR2_GRPMASK1 … /* SITSCR and SIRSCR */ #define SISCR_BRPS_MASK … #define SISCR_BRPS(i) … #define SISCR_BRDV_MASK … #define SISCR_BRDV_DIV_2 … #define SISCR_BRDV_DIV_4 … #define SISCR_BRDV_DIV_8 … #define SISCR_BRDV_DIV_16 … #define SISCR_BRDV_DIV_32 … #define SISCR_BRDV_DIV_1 … /* SICTR */ #define SICTR_TSCKIZ_MASK … #define SICTR_TSCKIZ_SCK … #define SICTR_TSCKIZ_POL_SHIFT … #define SICTR_RSCKIZ_MASK … #define SICTR_RSCKIZ_SCK … #define SICTR_RSCKIZ_POL_SHIFT … #define SICTR_TEDG_SHIFT … #define SICTR_REDG_SHIFT … #define SICTR_TXDIZ_MASK … #define SICTR_TXDIZ_LOW … #define SICTR_TXDIZ_HIGH … #define SICTR_TXDIZ_HIZ … #define SICTR_TSCKE … #define SICTR_TFSE … #define SICTR_TXE … #define SICTR_RXE … #define SICTR_TXRST … #define SICTR_RXRST … /* SIFCTR */ #define SIFCTR_TFWM_MASK … #define SIFCTR_TFWM_64 … #define SIFCTR_TFWM_32 … #define SIFCTR_TFWM_24 … #define SIFCTR_TFWM_16 … #define SIFCTR_TFWM_12 … #define SIFCTR_TFWM_8 … #define SIFCTR_TFWM_4 … #define SIFCTR_TFWM_1 … #define SIFCTR_TFUA_MASK … #define SIFCTR_TFUA_SHIFT … #define SIFCTR_TFUA(i) … #define SIFCTR_RFWM_MASK … #define SIFCTR_RFWM_1 … #define SIFCTR_RFWM_4 … #define SIFCTR_RFWM_8 … #define SIFCTR_RFWM_16 … #define SIFCTR_RFWM_32 … #define SIFCTR_RFWM_64 … #define SIFCTR_RFWM_128 … #define SIFCTR_RFWM_256 … #define SIFCTR_RFUA_MASK … #define SIFCTR_RFUA_SHIFT … #define SIFCTR_RFUA(i) … /* SISTR */ #define SISTR_TFEMP … #define SISTR_TDREQ … #define SISTR_TEOF … #define SISTR_TFSERR … #define SISTR_TFOVF … #define SISTR_TFUDF … #define SISTR_RFFUL … #define SISTR_RDREQ … #define SISTR_REOF … #define SISTR_RFSERR … #define SISTR_RFUDF … #define SISTR_RFOVF … /* SIIER */ #define SIIER_TDMAE … #define SIIER_TFEMPE … #define SIIER_TDREQE … #define SIIER_TEOFE … #define SIIER_TFSERRE … #define SIIER_TFOVFE … #define SIIER_TFUDFE … #define SIIER_RDMAE … #define SIIER_RFFULE … #define SIIER_RDREQE … #define SIIER_REOFE … #define SIIER_RFSERRE … #define SIIER_RFUDFE … #define SIIER_RFOVFE … static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) { … } static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, u32 value) { … } static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, u32 clr, u32 set) { … } static irqreturn_t sh_msiof_spi_irq(int irq, void *data) { … } static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p) { … } static const u32 sh_msiof_spi_div_array[] = …; static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, struct spi_transfer *t) { … } static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl) { … } static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p) { … } static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss, u32 cpol, u32 cpha, u32 tx_hi_z, u32 lsb_first, u32 cs_high) { … } static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, const void *tx_buf, void *rx_buf, u32 bits, u32 words) { … } static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) { … } static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, const void *tx_buf, int words, int fs) { … } static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, const void *tx_buf, int words, int fs) { … } static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, const void *tx_buf, int words, int fs) { … } static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, const void *tx_buf, int words, int fs) { … } static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, const void *tx_buf, int words, int fs) { … } static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, const void *tx_buf, int words, int fs) { … } static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, const void *tx_buf, int words, int fs) { … } static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, void *rx_buf, int words, int fs) { … } static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, void *rx_buf, int words, int fs) { … } static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, void *rx_buf, int words, int fs) { … } static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, void *rx_buf, int words, int fs) { … } static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, void *rx_buf, int words, int fs) { … } static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, void *rx_buf, int words, int fs) { … } static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, void *rx_buf, int words, int fs) { … } static int sh_msiof_spi_setup(struct spi_device *spi) { … } static int sh_msiof_prepare_message(struct spi_controller *ctlr, struct spi_message *msg) { … } static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf) { … } static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf) { … } static int sh_msiof_target_abort(struct spi_controller *ctlr) { … } static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p, struct completion *x) { … } static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int), void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int), const void *tx_buf, void *rx_buf, int words, int bits) { … } static void sh_msiof_dma_complete(void *arg) { … } static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, void *rx, unsigned int len) { … } static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words) { … } static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words) { … } static void copy_plain32(u32 *dst, const u32 *src, unsigned int words) { … } static int sh_msiof_transfer_one(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *t) { … } static const struct sh_msiof_chipdata sh_data = …; static const struct sh_msiof_chipdata rcar_gen2_data = …; static const struct sh_msiof_chipdata rcar_gen3_data = …; static const struct sh_msiof_chipdata rcar_r8a7795_data = …; static const struct of_device_id sh_msiof_match[] __maybe_unused = …; MODULE_DEVICE_TABLE(of, sh_msiof_match); #ifdef CONFIG_OF static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) { … } #else static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) { return NULL; } #endif static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev, enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr) { … } static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p) { … } static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p) { … } static int sh_msiof_spi_probe(struct platform_device *pdev) { … } static void sh_msiof_spi_remove(struct platform_device *pdev) { … } static const struct platform_device_id spi_driver_ids[] = …; MODULE_DEVICE_TABLE(platform, spi_driver_ids); #ifdef CONFIG_PM_SLEEP static int sh_msiof_spi_suspend(struct device *dev) { … } static int sh_msiof_spi_resume(struct device *dev) { … } static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend, sh_msiof_spi_resume); #define DEV_PM_OPS … #else #define DEV_PM_OPS … #endif /* CONFIG_PM_SLEEP */ static struct platform_driver sh_msiof_spi_drv = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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