/* * Copyright (C) 2017 Spreadtrum Communications Inc. * * SPDX-License-Identifier: GPL-2.0 */ #include <linux/delay.h> #include <linux/hwspinlock.h> #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/reboot.h> #include <linux/spi/spi.h> #include <linux/sizes.h> /* Registers definitions for ADI controller */ #define REG_ADI_CTRL0 … #define REG_ADI_CHN_PRIL … #define REG_ADI_CHN_PRIH … #define REG_ADI_INT_EN … #define REG_ADI_INT_RAW … #define REG_ADI_INT_MASK … #define REG_ADI_INT_CLR … #define REG_ADI_GSSI_CFG0 … #define REG_ADI_GSSI_CFG1 … #define REG_ADI_RD_CMD … #define REG_ADI_RD_DATA … #define REG_ADI_ARM_FIFO_STS … #define REG_ADI_STS … #define REG_ADI_EVT_FIFO_STS … #define REG_ADI_ARM_CMD_STS … #define REG_ADI_CHN_EN … #define REG_ADI_CHN_ADDR(id) … #define REG_ADI_CHN_EN1 … /* Bits definitions for register REG_ADI_GSSI_CFG0 */ #define BIT_CLK_ALL_ON … /* Bits definitions for register REG_ADI_RD_DATA */ #define BIT_RD_CMD_BUSY … #define RD_ADDR_SHIFT … #define RD_VALUE_MASK … #define RD_ADDR_MASK … /* Bits definitions for register REG_ADI_ARM_FIFO_STS */ #define BIT_FIFO_FULL … #define BIT_FIFO_EMPTY … /* * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on. * ADI supports 12/14bit address for r2p0, and additional 17bit for r3p0 or * later versions. Since bit[1:0] are zero, so the spec describe them as * 10/12/15bit address mode. * The 10bit mode supports sigle slave, 12/15bit mode supports 3 slave, the * high two bits is slave_id. * The slave devices address offset is 0x8000 for 10/12bit address mode, * and 0x20000 for 15bit mode. */ #define ADI_10BIT_SLAVE_ADDR_SIZE … #define ADI_10BIT_SLAVE_OFFSET … #define ADI_12BIT_SLAVE_ADDR_SIZE … #define ADI_12BIT_SLAVE_OFFSET … #define ADI_15BIT_SLAVE_ADDR_SIZE … #define ADI_15BIT_SLAVE_OFFSET … /* Timeout (ms) for the trylock of hardware spinlocks */ #define ADI_HWSPINLOCK_TIMEOUT … /* * ADI controller has 50 channels including 2 software channels * and 48 hardware channels. */ #define ADI_HW_CHNS … #define ADI_FIFO_DRAIN_TIMEOUT … #define ADI_READ_TIMEOUT … /* * Read back address from REG_ADI_RD_DATA bit[30:16] which maps to: * REG_ADI_RD_CMD bit[14:0] for r2p0 * REG_ADI_RD_CMD bit[16:2] for r3p0 */ #define RDBACK_ADDR_MASK_R2 … #define RDBACK_ADDR_MASK_R3 … #define RDBACK_ADDR_SHIFT_R3 … /* Registers definitions for PMIC watchdog controller */ #define REG_WDG_LOAD_LOW … #define REG_WDG_LOAD_HIGH … #define REG_WDG_CTRL … #define REG_WDG_LOCK … /* Bits definitions for register REG_WDG_CTRL */ #define BIT_WDG_RUN … #define BIT_WDG_NEW … #define BIT_WDG_RST … /* Bits definitions for register REG_MODULE_EN */ #define BIT_WDG_EN … /* Registers definitions for PMIC */ #define PMIC_RST_STATUS … #define PMIC_MODULE_EN … #define PMIC_CLK_EN … #define PMIC_WDG_BASE … /* Definition of PMIC reset status register */ #define HWRST_STATUS_SECURITY … #define HWRST_STATUS_RECOVERY … #define HWRST_STATUS_NORMAL … #define HWRST_STATUS_ALARM … #define HWRST_STATUS_SLEEP … #define HWRST_STATUS_FASTBOOT … #define HWRST_STATUS_SPECIAL … #define HWRST_STATUS_PANIC … #define HWRST_STATUS_CFTREBOOT … #define HWRST_STATUS_AUTODLOADER … #define HWRST_STATUS_IQMODE … #define HWRST_STATUS_SPRDISK … #define HWRST_STATUS_FACTORYTEST … #define HWRST_STATUS_WATCHDOG … /* Use default timeout 50 ms that converts to watchdog values */ #define WDG_LOAD_VAL … #define WDG_LOAD_MASK … #define WDG_UNLOCK_KEY … struct sprd_adi_wdg { … }; struct sprd_adi_data { … }; struct sprd_adi { … }; static int sprd_adi_check_addr(struct sprd_adi *sadi, u32 reg) { … } static int sprd_adi_drain_fifo(struct sprd_adi *sadi) { … } static int sprd_adi_fifo_is_full(struct sprd_adi *sadi) { … } static int sprd_adi_read_check(u32 val, u32 addr) { … } static int sprd_adi_read_check_r2(u32 val, u32 reg) { … } static int sprd_adi_read_check_r3(u32 val, u32 reg) { … } static int sprd_adi_read(struct sprd_adi *sadi, u32 reg, u32 *read_val) { … } static int sprd_adi_write(struct sprd_adi *sadi, u32 reg, u32 val) { … } static int sprd_adi_transfer_one(struct spi_controller *ctlr, struct spi_device *spi_dev, struct spi_transfer *t) { … } static void sprd_adi_set_wdt_rst_mode(void *p) { … } static int sprd_adi_restart(struct sprd_adi *sadi, unsigned long mode, const char *cmd, struct sprd_adi_wdg *wdg) { … } static int sprd_adi_restart_sc9860(struct sys_off_data *data) { … } static void sprd_adi_hw_init(struct sprd_adi *sadi) { … } static int sprd_adi_probe(struct platform_device *pdev) { … } static struct sprd_adi_data sc9860_data = …; static struct sprd_adi_data sc9863_data = …; static struct sprd_adi_data ums512_data = …; static const struct of_device_id sprd_adi_of_match[] = …; MODULE_DEVICE_TABLE(of, sprd_adi_of_match); static struct platform_driver sprd_adi_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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