// SPDX-License-Identifier: GPL-2.0 // // Synquacer HSSPI controller driver // // Copyright (c) 2015-2018 Socionext Inc. // Copyright (c) 2018-2019 Linaro Ltd. // #include <linux/acpi.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/scatterlist.h> #include <linux/slab.h> #include <linux/spi/spi.h> #include <linux/spinlock.h> #include <linux/clk.h> /* HSSPI register address definitions */ #define SYNQUACER_HSSPI_REG_MCTRL … #define SYNQUACER_HSSPI_REG_PCC0 … #define SYNQUACER_HSSPI_REG_PCC(n) … #define SYNQUACER_HSSPI_REG_TXF … #define SYNQUACER_HSSPI_REG_TXE … #define SYNQUACER_HSSPI_REG_TXC … #define SYNQUACER_HSSPI_REG_RXF … #define SYNQUACER_HSSPI_REG_RXE … #define SYNQUACER_HSSPI_REG_RXC … #define SYNQUACER_HSSPI_REG_FAULTF … #define SYNQUACER_HSSPI_REG_FAULTC … #define SYNQUACER_HSSPI_REG_DMCFG … #define SYNQUACER_HSSPI_REG_DMSTART … #define SYNQUACER_HSSPI_REG_DMBCC … #define SYNQUACER_HSSPI_REG_DMSTATUS … #define SYNQUACER_HSSPI_REG_FIFOCFG … #define SYNQUACER_HSSPI_REG_TX_FIFO … #define SYNQUACER_HSSPI_REG_RX_FIFO … #define SYNQUACER_HSSPI_REG_MID … /* HSSPI register bit definitions */ #define SYNQUACER_HSSPI_MCTRL_MEN … #define SYNQUACER_HSSPI_MCTRL_COMMAND_SEQUENCE_EN … #define SYNQUACER_HSSPI_MCTRL_CDSS … #define SYNQUACER_HSSPI_MCTRL_MES … #define SYNQUACER_HSSPI_MCTRL_SYNCON … #define SYNQUACER_HSSPI_PCC_CPHA … #define SYNQUACER_HSSPI_PCC_CPOL … #define SYNQUACER_HSSPI_PCC_ACES … #define SYNQUACER_HSSPI_PCC_RTM … #define SYNQUACER_HSSPI_PCC_SSPOL … #define SYNQUACER_HSSPI_PCC_SDIR … #define SYNQUACER_HSSPI_PCC_SENDIAN … #define SYNQUACER_HSSPI_PCC_SAFESYNC … #define SYNQUACER_HSSPI_PCC_SS2CD_SHIFT … #define SYNQUACER_HSSPI_PCC_CDRS_MASK … #define SYNQUACER_HSSPI_PCC_CDRS_SHIFT … #define SYNQUACER_HSSPI_TXF_FIFO_FULL … #define SYNQUACER_HSSPI_TXF_FIFO_EMPTY … #define SYNQUACER_HSSPI_TXF_SLAVE_RELEASED … #define SYNQUACER_HSSPI_TXE_FIFO_FULL … #define SYNQUACER_HSSPI_TXE_FIFO_EMPTY … #define SYNQUACER_HSSPI_TXE_SLAVE_RELEASED … #define SYNQUACER_HSSPI_RXF_FIFO_MORE_THAN_THRESHOLD … #define SYNQUACER_HSSPI_RXF_SLAVE_RELEASED … #define SYNQUACER_HSSPI_RXE_FIFO_MORE_THAN_THRESHOLD … #define SYNQUACER_HSSPI_RXE_SLAVE_RELEASED … #define SYNQUACER_HSSPI_DMCFG_SSDC … #define SYNQUACER_HSSPI_DMCFG_MSTARTEN … #define SYNQUACER_HSSPI_DMSTART_START … #define SYNQUACER_HSSPI_DMSTOP_STOP … #define SYNQUACER_HSSPI_DMPSEL_CS_MASK … #define SYNQUACER_HSSPI_DMPSEL_CS_SHIFT … #define SYNQUACER_HSSPI_DMTRP_BUS_WIDTH_SHIFT … #define SYNQUACER_HSSPI_DMTRP_DATA_MASK … #define SYNQUACER_HSSPI_DMTRP_DATA_SHIFT … #define SYNQUACER_HSSPI_DMTRP_DATA_TXRX … #define SYNQUACER_HSSPI_DMTRP_DATA_RX … #define SYNQUACER_HSSPI_DMTRP_DATA_TX … #define SYNQUACER_HSSPI_DMSTATUS_RX_DATA_MASK … #define SYNQUACER_HSSPI_DMSTATUS_RX_DATA_SHIFT … #define SYNQUACER_HSSPI_DMSTATUS_TX_DATA_MASK … #define SYNQUACER_HSSPI_DMSTATUS_TX_DATA_SHIFT … #define SYNQUACER_HSSPI_FIFOCFG_RX_THRESHOLD_MASK … #define SYNQUACER_HSSPI_FIFOCFG_RX_THRESHOLD_SHIFT … #define SYNQUACER_HSSPI_FIFOCFG_TX_THRESHOLD_MASK … #define SYNQUACER_HSSPI_FIFOCFG_TX_THRESHOLD_SHIFT … #define SYNQUACER_HSSPI_FIFOCFG_FIFO_WIDTH_MASK … #define SYNQUACER_HSSPI_FIFOCFG_FIFO_WIDTH_SHIFT … #define SYNQUACER_HSSPI_FIFOCFG_RX_FLUSH … #define SYNQUACER_HSSPI_FIFOCFG_TX_FLUSH … #define SYNQUACER_HSSPI_FIFO_DEPTH … #define SYNQUACER_HSSPI_FIFO_TX_THRESHOLD … #define SYNQUACER_HSSPI_FIFO_RX_THRESHOLD … #define SYNQUACER_HSSPI_TRANSFER_MODE_TX … #define SYNQUACER_HSSPI_TRANSFER_MODE_RX … #define SYNQUACER_HSSPI_TRANSFER_TMOUT_MSEC … #define SYNQUACER_HSSPI_ENABLE_TMOUT_MSEC … #define SYNQUACER_HSSPI_CLOCK_SRC_IHCLK … #define SYNQUACER_HSSPI_CLOCK_SRC_IPCLK … #define SYNQUACER_HSSPI_NUM_CHIP_SELECT … #define SYNQUACER_HSSPI_IRQ_NAME_MAX … struct synquacer_spi { … }; static int read_fifo(struct synquacer_spi *sspi) { … } static int write_fifo(struct synquacer_spi *sspi) { … } static int synquacer_spi_config(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *xfer) { … } static int synquacer_spi_transfer_one(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *xfer) { … } static void synquacer_spi_set_cs(struct spi_device *spi, bool enable) { … } static int synquacer_spi_wait_status_update(struct synquacer_spi *sspi, bool enable) { … } static int synquacer_spi_enable(struct spi_controller *host) { … } static irqreturn_t sq_spi_rx_handler(int irq, void *priv) { … } static irqreturn_t sq_spi_tx_handler(int irq, void *priv) { … } static int synquacer_spi_probe(struct platform_device *pdev) { … } static void synquacer_spi_remove(struct platform_device *pdev) { … } static int __maybe_unused synquacer_spi_suspend(struct device *dev) { … } static int __maybe_unused synquacer_spi_resume(struct device *dev) { … } static SIMPLE_DEV_PM_OPS(synquacer_spi_pm_ops, synquacer_spi_suspend, synquacer_spi_resume); static const struct of_device_id synquacer_spi_of_match[] = …; MODULE_DEVICE_TABLE(of, synquacer_spi_of_match); #ifdef CONFIG_ACPI static const struct acpi_device_id synquacer_hsspi_acpi_ids[] = …; MODULE_DEVICE_TABLE(acpi, synquacer_hsspi_acpi_ids); #endif static struct platform_driver synquacer_spi_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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