// SPDX-License-Identifier: GPL-2.0-only // // Copyright (C) 2020 NVIDIA CORPORATION. #include <linux/clk.h> #include <linux/completion.h> #include <linux/delay.h> #include <linux/dmaengine.h> #include <linux/dma-mapping.h> #include <linux/dmapool.h> #include <linux/err.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/kthread.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/of.h> #include <linux/reset.h> #include <linux/spi/spi.h> #include <linux/acpi.h> #include <linux/property.h> #define QSPI_COMMAND1 … #define QSPI_BIT_LENGTH(x) … #define QSPI_PACKED … #define QSPI_INTERFACE_WIDTH_MASK … #define QSPI_INTERFACE_WIDTH(x) … #define QSPI_INTERFACE_WIDTH_SINGLE … #define QSPI_INTERFACE_WIDTH_DUAL … #define QSPI_INTERFACE_WIDTH_QUAD … #define QSPI_SDR_DDR_SEL … #define QSPI_TX_EN … #define QSPI_RX_EN … #define QSPI_CS_SW_VAL … #define QSPI_CS_SW_HW … #define QSPI_CS_POL_INACTIVE(n) … #define QSPI_CS_POL_INACTIVE_MASK … #define QSPI_CS_SEL_0 … #define QSPI_CS_SEL_1 … #define QSPI_CS_SEL_2 … #define QSPI_CS_SEL_3 … #define QSPI_CS_SEL_MASK … #define QSPI_CS_SEL(x) … #define QSPI_CONTROL_MODE_0 … #define QSPI_CONTROL_MODE_3 … #define QSPI_CONTROL_MODE_MASK … #define QSPI_M_S … #define QSPI_PIO … #define QSPI_COMMAND2 … #define QSPI_TX_TAP_DELAY(x) … #define QSPI_RX_TAP_DELAY(x) … #define QSPI_CS_TIMING1 … #define QSPI_SETUP_HOLD(setup, hold) … #define QSPI_CS_TIMING2 … #define CYCLES_BETWEEN_PACKETS_0(x) … #define CS_ACTIVE_BETWEEN_PACKETS_0 … #define QSPI_TRANS_STATUS … #define QSPI_BLK_CNT(val) … #define QSPI_RDY … #define QSPI_FIFO_STATUS … #define QSPI_RX_FIFO_EMPTY … #define QSPI_RX_FIFO_FULL … #define QSPI_TX_FIFO_EMPTY … #define QSPI_TX_FIFO_FULL … #define QSPI_RX_FIFO_UNF … #define QSPI_RX_FIFO_OVF … #define QSPI_TX_FIFO_UNF … #define QSPI_TX_FIFO_OVF … #define QSPI_ERR … #define QSPI_TX_FIFO_FLUSH … #define QSPI_RX_FIFO_FLUSH … #define QSPI_TX_FIFO_EMPTY_COUNT(val) … #define QSPI_RX_FIFO_FULL_COUNT(val) … #define QSPI_FIFO_ERROR … #define QSPI_FIFO_EMPTY … #define QSPI_TX_DATA … #define QSPI_RX_DATA … #define QSPI_DMA_CTL … #define QSPI_TX_TRIG(n) … #define QSPI_TX_TRIG_1 … #define QSPI_TX_TRIG_4 … #define QSPI_TX_TRIG_8 … #define QSPI_TX_TRIG_16 … #define QSPI_RX_TRIG(n) … #define QSPI_RX_TRIG_1 … #define QSPI_RX_TRIG_4 … #define QSPI_RX_TRIG_8 … #define QSPI_RX_TRIG_16 … #define QSPI_DMA_EN … #define QSPI_DMA_BLK … #define QSPI_DMA_BLK_SET(x) … #define QSPI_TX_FIFO … #define QSPI_RX_FIFO … #define QSPI_FIFO_DEPTH … #define QSPI_INTR_MASK … #define QSPI_INTR_RX_FIFO_UNF_MASK … #define QSPI_INTR_RX_FIFO_OVF_MASK … #define QSPI_INTR_TX_FIFO_UNF_MASK … #define QSPI_INTR_TX_FIFO_OVF_MASK … #define QSPI_INTR_RDY_MASK … #define QSPI_INTR_RX_TX_FIFO_ERR … #define QSPI_MISC_REG … #define QSPI_NUM_DUMMY_CYCLE(x) … #define QSPI_DUMMY_CYCLES_MAX … #define QSPI_CMB_SEQ_CMD … #define QSPI_COMMAND_VALUE_SET(X) … #define QSPI_CMB_SEQ_CMD_CFG … #define QSPI_COMMAND_X1_X2_X4(x) … #define QSPI_COMMAND_X1_X2_X4_MASK … #define QSPI_COMMAND_SDR_DDR … #define QSPI_COMMAND_SIZE_SET(x) … #define QSPI_GLOBAL_CONFIG … #define QSPI_CMB_SEQ_EN … #define QSPI_TPM_WAIT_POLL_EN … #define QSPI_CMB_SEQ_ADDR … #define QSPI_ADDRESS_VALUE_SET(X) … #define QSPI_CMB_SEQ_ADDR_CFG … #define QSPI_ADDRESS_X1_X2_X4(x) … #define QSPI_ADDRESS_X1_X2_X4_MASK … #define QSPI_ADDRESS_SDR_DDR … #define QSPI_ADDRESS_SIZE_SET(x) … #define DATA_DIR_TX … #define DATA_DIR_RX … #define QSPI_DMA_TIMEOUT … #define DEFAULT_QSPI_DMA_BUF_LEN … #define CMD_TRANSFER … #define ADDR_TRANSFER … #define DATA_TRANSFER … struct tegra_qspi_soc_data { … }; struct tegra_qspi_client_data { … }; struct tegra_qspi { … }; static inline u32 tegra_qspi_readl(struct tegra_qspi *tqspi, unsigned long offset) { … } static inline void tegra_qspi_writel(struct tegra_qspi *tqspi, u32 value, unsigned long offset) { … } static void tegra_qspi_mask_clear_irq(struct tegra_qspi *tqspi) { … } static unsigned int tegra_qspi_calculate_curr_xfer_param(struct tegra_qspi *tqspi, struct spi_transfer *t) { … } static unsigned int tegra_qspi_fill_tx_fifo_from_client_txbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) { … } static unsigned int tegra_qspi_read_rx_fifo_to_client_rxbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) { … } static void tegra_qspi_copy_client_txbuf_to_qspi_txbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) { … } static void tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) { … } static void tegra_qspi_dma_complete(void *args) { … } static int tegra_qspi_start_tx_dma(struct tegra_qspi *tqspi, struct spi_transfer *t, int len) { … } static int tegra_qspi_start_rx_dma(struct tegra_qspi *tqspi, struct spi_transfer *t, int len) { … } static int tegra_qspi_flush_fifos(struct tegra_qspi *tqspi, bool atomic) { … } static void tegra_qspi_unmask_irq(struct tegra_qspi *tqspi) { … } static int tegra_qspi_dma_map_xfer(struct tegra_qspi *tqspi, struct spi_transfer *t) { … } static void tegra_qspi_dma_unmap_xfer(struct tegra_qspi *tqspi, struct spi_transfer *t) { … } static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct spi_transfer *t) { … } static int tegra_qspi_start_cpu_based_transfer(struct tegra_qspi *qspi, struct spi_transfer *t) { … } static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi) { … } static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) { … } static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_transfer *t, bool is_first_of_msg) { … } static int tegra_qspi_start_transfer_one(struct spi_device *spi, struct spi_transfer *t, u32 command1) { … } static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_device *spi) { … } static int tegra_qspi_setup(struct spi_device *spi) { … } static void tegra_qspi_dump_regs(struct tegra_qspi *tqspi) { … } static void tegra_qspi_handle_error(struct tegra_qspi *tqspi) { … } static void tegra_qspi_transfer_end(struct spi_device *spi) { … } static u32 tegra_qspi_cmd_config(bool is_ddr, u8 bus_width, u8 len) { … } static u32 tegra_qspi_addr_config(bool is_ddr, u8 bus_width, u8 len) { … } static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, struct spi_message *msg) { … } static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, struct spi_message *msg) { … } static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi, struct spi_message *msg) { … } static int tegra_qspi_transfer_one_message(struct spi_controller *host, struct spi_message *msg) { … } static irqreturn_t handle_cpu_based_xfer(struct tegra_qspi *tqspi) { … } static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi) { … } static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data) { … } static struct tegra_qspi_soc_data tegra210_qspi_soc_data = …; static struct tegra_qspi_soc_data tegra186_qspi_soc_data = …; static struct tegra_qspi_soc_data tegra234_qspi_soc_data = …; static struct tegra_qspi_soc_data tegra241_qspi_soc_data = …; static const struct of_device_id tegra_qspi_of_match[] = …; MODULE_DEVICE_TABLE(of, tegra_qspi_of_match); #ifdef CONFIG_ACPI static const struct acpi_device_id tegra_qspi_acpi_match[] = …; MODULE_DEVICE_TABLE(acpi, tegra_qspi_acpi_match); #endif static int tegra_qspi_probe(struct platform_device *pdev) { … } static void tegra_qspi_remove(struct platform_device *pdev) { … } static int __maybe_unused tegra_qspi_suspend(struct device *dev) { … } static int __maybe_unused tegra_qspi_resume(struct device *dev) { … } static int __maybe_unused tegra_qspi_runtime_suspend(struct device *dev) { … } static int __maybe_unused tegra_qspi_runtime_resume(struct device *dev) { … } static const struct dev_pm_ops tegra_qspi_pm_ops = …; static struct platform_driver tegra_qspi_driver = …; module_platform_driver(…) …; MODULE_ALIAS(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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