// SPDX-License-Identifier: GPL-2.0-only /* * SPI driver for NVIDIA's Tegra114 SPI Controller. * * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. */ #include <linux/clk.h> #include <linux/completion.h> #include <linux/delay.h> #include <linux/dmaengine.h> #include <linux/dma-mapping.h> #include <linux/dmapool.h> #include <linux/err.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/kthread.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/of.h> #include <linux/reset.h> #include <linux/spi/spi.h> #define SPI_COMMAND1 … #define SPI_BIT_LENGTH(x) … #define SPI_PACKED … #define SPI_TX_EN … #define SPI_RX_EN … #define SPI_BOTH_EN_BYTE … #define SPI_BOTH_EN_BIT … #define SPI_LSBYTE_FE … #define SPI_LSBIT_FE … #define SPI_BIDIROE … #define SPI_IDLE_SDA_DRIVE_LOW … #define SPI_IDLE_SDA_DRIVE_HIGH … #define SPI_IDLE_SDA_PULL_LOW … #define SPI_IDLE_SDA_PULL_HIGH … #define SPI_IDLE_SDA_MASK … #define SPI_CS_SW_VAL … #define SPI_CS_SW_HW … /* SPI_CS_POL_INACTIVE bits are default high */ /* n from 0 to 3 */ #define SPI_CS_POL_INACTIVE(n) … #define SPI_CS_POL_INACTIVE_MASK … #define SPI_CS_SEL_0 … #define SPI_CS_SEL_1 … #define SPI_CS_SEL_2 … #define SPI_CS_SEL_3 … #define SPI_CS_SEL_MASK … #define SPI_CS_SEL(x) … #define SPI_CONTROL_MODE_0 … #define SPI_CONTROL_MODE_1 … #define SPI_CONTROL_MODE_2 … #define SPI_CONTROL_MODE_3 … #define SPI_CONTROL_MODE_MASK … #define SPI_MODE_SEL(x) … #define SPI_M_S … #define SPI_PIO … #define SPI_COMMAND2 … #define SPI_TX_TAP_DELAY(x) … #define SPI_RX_TAP_DELAY(x) … #define SPI_CS_TIMING1 … #define SPI_SETUP_HOLD(setup, hold) … #define SPI_CS_SETUP_HOLD(reg, cs, val) … #define SPI_CS_TIMING2 … #define CYCLES_BETWEEN_PACKETS_0(x) … #define CS_ACTIVE_BETWEEN_PACKETS_0 … #define CYCLES_BETWEEN_PACKETS_1(x) … #define CS_ACTIVE_BETWEEN_PACKETS_1 … #define CYCLES_BETWEEN_PACKETS_2(x) … #define CS_ACTIVE_BETWEEN_PACKETS_2 … #define CYCLES_BETWEEN_PACKETS_3(x) … #define CS_ACTIVE_BETWEEN_PACKETS_3 … #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) … #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) … #define MAX_SETUP_HOLD_CYCLES … #define MAX_INACTIVE_CYCLES … #define SPI_TRANS_STATUS … #define SPI_BLK_CNT(val) … #define SPI_SLV_IDLE_COUNT(val) … #define SPI_RDY … #define SPI_FIFO_STATUS … #define SPI_RX_FIFO_EMPTY … #define SPI_RX_FIFO_FULL … #define SPI_TX_FIFO_EMPTY … #define SPI_TX_FIFO_FULL … #define SPI_RX_FIFO_UNF … #define SPI_RX_FIFO_OVF … #define SPI_TX_FIFO_UNF … #define SPI_TX_FIFO_OVF … #define SPI_ERR … #define SPI_TX_FIFO_FLUSH … #define SPI_RX_FIFO_FLUSH … #define SPI_TX_FIFO_EMPTY_COUNT(val) … #define SPI_RX_FIFO_FULL_COUNT(val) … #define SPI_FRAME_END … #define SPI_CS_INACTIVE … #define SPI_FIFO_ERROR … #define SPI_FIFO_EMPTY … #define SPI_TX_DATA … #define SPI_RX_DATA … #define SPI_DMA_CTL … #define SPI_TX_TRIG_1 … #define SPI_TX_TRIG_4 … #define SPI_TX_TRIG_8 … #define SPI_TX_TRIG_16 … #define SPI_TX_TRIG_MASK … #define SPI_RX_TRIG_1 … #define SPI_RX_TRIG_4 … #define SPI_RX_TRIG_8 … #define SPI_RX_TRIG_16 … #define SPI_RX_TRIG_MASK … #define SPI_IE_TX … #define SPI_IE_RX … #define SPI_CONT … #define SPI_DMA … #define SPI_DMA_EN … #define SPI_DMA_BLK … #define SPI_DMA_BLK_SET(x) … #define SPI_TX_FIFO … #define SPI_RX_FIFO … #define SPI_INTR_MASK … #define SPI_INTR_ALL_MASK … #define MAX_CHIP_SELECT … #define SPI_FIFO_DEPTH … #define DATA_DIR_TX … #define DATA_DIR_RX … #define SPI_DMA_TIMEOUT … #define DEFAULT_SPI_DMA_BUF_LEN … #define TX_FIFO_EMPTY_COUNT_MAX … #define RX_FIFO_FULL_COUNT_ZERO … #define MAX_HOLD_CYCLES … #define SPI_DEFAULT_SPEED … struct tegra_spi_soc_data { … }; struct tegra_spi_client_data { … }; struct tegra_spi_data { … }; static int tegra_spi_runtime_suspend(struct device *dev); static int tegra_spi_runtime_resume(struct device *dev); static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi, unsigned long reg) { … } static inline void tegra_spi_writel(struct tegra_spi_data *tspi, u32 val, unsigned long reg) { … } static void tegra_spi_clear_status(struct tegra_spi_data *tspi) { … } static unsigned tegra_spi_calculate_curr_xfer_param( struct spi_device *spi, struct tegra_spi_data *tspi, struct spi_transfer *t) { … } static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf( struct tegra_spi_data *tspi, struct spi_transfer *t) { … } static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf( struct tegra_spi_data *tspi, struct spi_transfer *t) { … } static void tegra_spi_copy_client_txbuf_to_spi_txbuf( struct tegra_spi_data *tspi, struct spi_transfer *t) { … } static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf( struct tegra_spi_data *tspi, struct spi_transfer *t) { … } static void tegra_spi_dma_complete(void *args) { … } static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len) { … } static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len) { … } static int tegra_spi_flush_fifos(struct tegra_spi_data *tspi) { … } static int tegra_spi_start_dma_based_transfer( struct tegra_spi_data *tspi, struct spi_transfer *t) { … } static int tegra_spi_start_cpu_based_transfer( struct tegra_spi_data *tspi, struct spi_transfer *t) { … } static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi, bool dma_to_memory) { … } static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi, bool dma_to_memory) { … } static int tegra_spi_set_hw_cs_timing(struct spi_device *spi) { … } static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, struct spi_transfer *t, bool is_first_of_msg, bool is_single_xfer) { … } static int tegra_spi_start_transfer_one(struct spi_device *spi, struct spi_transfer *t, u32 command1) { … } static struct tegra_spi_client_data *tegra_spi_parse_cdata_dt(struct spi_device *spi) { … } static void tegra_spi_cleanup(struct spi_device *spi) { … } static int tegra_spi_setup(struct spi_device *spi) { … } static void tegra_spi_transfer_end(struct spi_device *spi) { … } static void tegra_spi_dump_regs(struct tegra_spi_data *tspi) { … } static int tegra_spi_transfer_one_message(struct spi_controller *host, struct spi_message *msg) { … } static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi) { … } static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi) { … } static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data) { … } static irqreturn_t tegra_spi_isr(int irq, void *context_data) { … } static struct tegra_spi_soc_data tegra114_spi_soc_data = …; static struct tegra_spi_soc_data tegra124_spi_soc_data = …; static struct tegra_spi_soc_data tegra210_spi_soc_data = …; static const struct of_device_id tegra_spi_of_match[] = …; MODULE_DEVICE_TABLE(of, tegra_spi_of_match); static int tegra_spi_probe(struct platform_device *pdev) { … } static void tegra_spi_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int tegra_spi_suspend(struct device *dev) { … } static int tegra_spi_resume(struct device *dev) { … } #endif static int tegra_spi_runtime_suspend(struct device *dev) { … } static int tegra_spi_runtime_resume(struct device *dev) { … } static const struct dev_pm_ops tegra_spi_pm_ops = …; static struct platform_driver tegra_spi_driver = …; module_platform_driver(…) …; MODULE_ALIAS(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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