// SPDX-License-Identifier: GPL-2.0-only /* * Xilinx SPI controller driver (host mode only) * * Author: MontaVista Software, Inc. * [email protected] * * Copyright (c) 2010 Secret Lab Technologies, Ltd. * Copyright (c) 2009 Intel Corporation * 2002-2007 (c) MontaVista Software, Inc. */ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/spi/spi.h> #include <linux/spi/spi_bitbang.h> #include <linux/spi/xilinx_spi.h> #include <linux/io.h> #define XILINX_SPI_MAX_CS … #define XILINX_SPI_NAME … /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) * Product Specification", DS464 */ #define XSPI_CR_OFFSET … #define XSPI_CR_LOOP … #define XSPI_CR_ENABLE … #define XSPI_CR_MASTER_MODE … #define XSPI_CR_CPOL … #define XSPI_CR_CPHA … #define XSPI_CR_MODE_MASK … #define XSPI_CR_TXFIFO_RESET … #define XSPI_CR_RXFIFO_RESET … #define XSPI_CR_MANUAL_SSELECT … #define XSPI_CR_TRANS_INHIBIT … #define XSPI_CR_LSB_FIRST … #define XSPI_SR_OFFSET … #define XSPI_SR_RX_EMPTY_MASK … #define XSPI_SR_RX_FULL_MASK … #define XSPI_SR_TX_EMPTY_MASK … #define XSPI_SR_TX_FULL_MASK … #define XSPI_SR_MODE_FAULT_MASK … #define XSPI_TXD_OFFSET … #define XSPI_RXD_OFFSET … #define XSPI_SSR_OFFSET … /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 * IPIF registers are 32 bit */ #define XIPIF_V123B_DGIER_OFFSET … #define XIPIF_V123B_GINTR_ENABLE … #define XIPIF_V123B_IISR_OFFSET … #define XIPIF_V123B_IIER_OFFSET … #define XSPI_INTR_MODE_FAULT … #define XSPI_INTR_SLAVE_MODE_FAULT … #define XSPI_INTR_TX_EMPTY … #define XSPI_INTR_TX_UNDERRUN … #define XSPI_INTR_RX_FULL … #define XSPI_INTR_RX_OVERRUN … #define XSPI_INTR_TX_HALF_EMPTY … #define XIPIF_V123B_RESETR_OFFSET … #define XIPIF_V123B_RESET_MASK … struct xilinx_spi { … }; static void xspi_write32(u32 val, void __iomem *addr) { … } static unsigned int xspi_read32(void __iomem *addr) { … } static void xspi_write32_be(u32 val, void __iomem *addr) { … } static unsigned int xspi_read32_be(void __iomem *addr) { … } static void xilinx_spi_tx(struct xilinx_spi *xspi) { … } static void xilinx_spi_rx(struct xilinx_spi *xspi) { … } static void xspi_init_hw(struct xilinx_spi *xspi) { … } static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) { … } /* spi_bitbang requires custom setup_transfer() to be defined if there is a * custom txrx_bufs(). */ static int xilinx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) { … } static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) { … } /* This driver supports single host mode only. Hence Tx FIFO Empty * is the only interrupt we care about. * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Target Mode * Fault are not to happen. */ static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) { … } static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi) { … } static const struct of_device_id xilinx_spi_of_match[] = …; MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); static int xilinx_spi_probe(struct platform_device *pdev) { … } static void xilinx_spi_remove(struct platform_device *pdev) { … } /* work with hotplug and coldplug */ MODULE_ALIAS(…) …; static struct platform_driver xilinx_spi_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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