#ifndef _MSCC_SERDES_PHY_H_
#define _MSCC_SERDES_PHY_H_
#define PHY_S6G_PLL5G_CFG2_GAIN_MASK …
#define PHY_S6G_PLL5G_CFG2_ENA_GAIN …
#define PHY_S6G_DES_PHY_CTRL_POS …
#define PHY_S6G_DES_MBTR_CTRL_POS …
#define PHY_S6G_DES_CPMD_SEL_POS …
#define PHY_S6G_DES_BW_HYST_POS …
#define PHY_S6G_DES_BW_ANA_POS …
#define PHY_S6G_DES_CFG …
#define PHY_S6G_IB_CFG0 …
#define PHY_S6G_IB_CFG1 …
#define PHY_S6G_IB_CFG2 …
#define PHY_S6G_IB_CFG3 …
#define PHY_S6G_IB_CFG4 …
#define PHY_S6G_GP_CFG …
#define PHY_S6G_DFT_CFG0 …
#define PHY_S6G_IB_DFT_CFG2 …
int vsc85xx_sd6g_config_v2(struct phy_device *phydev);
#endif