/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Driver for Microsemi VSC85xx PHYs * * Copyright (c) 2016 Microsemi Corporation */ #ifndef _MSCC_PHY_H_ #define _MSCC_PHY_H_ #if IS_ENABLED(CONFIG_MACSEC) #include "mscc_macsec.h" #endif enum rgmii_clock_delay { … }; /* Microsemi VSC85xx PHY registers */ /* IEEE 802. Std Registers */ #define MSCC_PHY_BYPASS_CONTROL … #define DISABLE_HP_AUTO_MDIX_MASK … #define DISABLE_PAIR_SWAP_CORR_MASK … #define DISABLE_POLARITY_CORR_MASK … #define PARALLEL_DET_IGNORE_ADVERTISED … #define MSCC_PHY_EXT_CNTL_STATUS … #define SMI_BROADCAST_WR_EN … #define MSCC_PHY_ERR_RX_CNT … #define MSCC_PHY_ERR_FALSE_CARRIER_CNT … #define MSCC_PHY_ERR_LINK_DISCONNECT_CNT … #define ERR_CNT_MASK … #define MSCC_PHY_EXT_PHY_CNTL_1 … #define MAC_IF_SELECTION_MASK … #define MAC_IF_SELECTION_GMII … #define MAC_IF_SELECTION_RMII … #define MAC_IF_SELECTION_RGMII … #define MAC_IF_SELECTION_POS … #define VSC8584_MAC_IF_SELECTION_MASK … #define VSC8584_MAC_IF_SELECTION_SGMII … #define VSC8584_MAC_IF_SELECTION_1000BASEX … #define VSC8584_MAC_IF_SELECTION_POS … #define FAR_END_LOOPBACK_MODE_MASK … #define MEDIA_OP_MODE_MASK … #define MEDIA_OP_MODE_COPPER … #define MEDIA_OP_MODE_SERDES … #define MEDIA_OP_MODE_1000BASEX … #define MEDIA_OP_MODE_100BASEFX … #define MEDIA_OP_MODE_AMS_COPPER_SERDES … #define MEDIA_OP_MODE_AMS_COPPER_1000BASEX … #define MEDIA_OP_MODE_AMS_COPPER_100BASEFX … #define MEDIA_OP_MODE_POS … #define MSCC_PHY_EXT_PHY_CNTL_2 … #define MII_VSC85XX_INT_MASK … #define MII_VSC85XX_INT_MASK_MDINT … #define MII_VSC85XX_INT_MASK_LINK_CHG … #define MII_VSC85XX_INT_MASK_WOL … #define MII_VSC85XX_INT_MASK_EXT … #define MII_VSC85XX_INT_STATUS … #define MII_VSC85XX_INT_MASK_MASK … #define MSCC_PHY_WOL_MAC_CONTROL … #define EDGE_RATE_CNTL_POS … #define EDGE_RATE_CNTL_MASK … #define MSCC_PHY_DEV_AUX_CNTL … #define HP_AUTO_MDIX_X_OVER_IND_MASK … #define MSCC_PHY_LED_MODE_SEL … #define LED_MODE_SEL_POS(x) … #define LED_MODE_SEL_MASK(x) … #define LED_MODE_SEL(x, mode) … #define MSCC_EXT_PAGE_CSR_CNTL_17 … #define MSCC_EXT_PAGE_CSR_CNTL_18 … #define MSCC_EXT_PAGE_CSR_CNTL_19 … #define MSCC_PHY_CSR_CNTL_19_REG_ADDR(x) … #define MSCC_PHY_CSR_CNTL_19_TARGET(x) … #define MSCC_PHY_CSR_CNTL_19_READ … #define MSCC_PHY_CSR_CNTL_19_CMD … #define MSCC_EXT_PAGE_CSR_CNTL_20 … #define MSCC_PHY_CSR_CNTL_20_TARGET(x) … #define PHY_MCB_TARGET … #define PHY_MCB_S6G_WRITE … #define PHY_MCB_S6G_READ … #define PHY_S6G_PLL5G_CFG0 … #define PHY_S6G_PLL5G_CFG2 … #define PHY_S6G_LCPLL_CFG … #define PHY_S6G_PLL_CFG … #define PHY_S6G_COMMON_CFG … #define PHY_S6G_GPC_CFG … #define PHY_S6G_MISC_CFG … #define PHY_MCB_S6G_CFG … #define PHY_S6G_DFT_CFG2 … #define PHY_S6G_PLL_STATUS … #define PHY_S6G_IB_STATUS0 … #define PHY_S6G_SYS_RST_POS … #define PHY_S6G_ENA_LANE_POS … #define PHY_S6G_ENA_LOOP_POS … #define PHY_S6G_QRATE_POS … #define PHY_S6G_IF_MODE_POS … #define PHY_S6G_PLL_ENA_OFFS_POS … #define PHY_S6G_PLL_FSM_CTRL_DATA_POS … #define PHY_S6G_PLL_FSM_ENA_POS … #define PHY_S6G_CFG2_FSM_DIS … #define PHY_S6G_CFG2_FSM_CLK_BP … #define MSCC_EXT_PAGE_ACCESS … #define MSCC_PHY_PAGE_STANDARD … #define MSCC_PHY_PAGE_EXTENDED … #define MSCC_PHY_PAGE_EXTENDED_2 … #define MSCC_PHY_PAGE_EXTENDED_3 … #define MSCC_PHY_PAGE_EXTENDED_4 … #define MSCC_PHY_PAGE_CSR_CNTL … #define MSCC_PHY_PAGE_MACSEC … /* Extended reg - GPIO; this is a bank of registers that are shared for all PHYs * in the same package. */ #define MSCC_PHY_PAGE_EXTENDED_GPIO … #define MSCC_PHY_PAGE_1588 … #define MSCC_PHY_PAGE_TEST … #define MSCC_PHY_PAGE_TR … #define MSCC_PHY_GPIO_CONTROL_2 … #define MSCC_PHY_COMA_MODE … #define MSCC_PHY_COMA_OUTPUT … /* Extended Page 1 Registers */ #define MSCC_PHY_CU_MEDIA_CRC_VALID_CNT … #define VALID_CRC_CNT_CRC_MASK … #define MSCC_PHY_EXT_MODE_CNTL … #define FORCE_MDI_CROSSOVER_MASK … #define FORCE_MDI_CROSSOVER_MDIX … #define FORCE_MDI_CROSSOVER_MDI … #define MSCC_PHY_ACTIPHY_CNTL … #define PHY_ADDR_REVERSED … #define DOWNSHIFT_CNTL_MASK … #define DOWNSHIFT_EN … #define DOWNSHIFT_CNTL_POS … #define MSCC_PHY_EXT_PHY_CNTL_4 … #define PHY_CNTL_4_ADDR_POS … #define MSCC_PHY_VERIPHY_CNTL_2 … #define MSCC_PHY_VERIPHY_CNTL_3 … /* Extended Page 2 Registers */ #define MSCC_PHY_CU_PMD_TX_CNTL … /* RGMII setting controls at address 18E2, for VSC8572 and similar */ #define VSC8572_RGMII_CNTL … #define VSC8572_RGMII_RX_DELAY_MASK … #define VSC8572_RGMII_TX_DELAY_MASK … /* RGMII controls at address 20E2, for VSC8502 and similar */ #define VSC8502_RGMII_CNTL … #define VSC8502_RGMII_RX_DELAY_MASK … #define VSC8502_RGMII_TX_DELAY_MASK … #define VSC8502_RGMII_RX_CLK_DISABLE … #define MSCC_PHY_WOL_LOWER_MAC_ADDR … #define MSCC_PHY_WOL_MID_MAC_ADDR … #define MSCC_PHY_WOL_UPPER_MAC_ADDR … #define MSCC_PHY_WOL_LOWER_PASSWD … #define MSCC_PHY_WOL_MID_PASSWD … #define MSCC_PHY_WOL_UPPER_PASSWD … #define MSCC_PHY_WOL_MAC_CONTROL … #define SECURE_ON_ENABLE … #define SECURE_ON_PASSWD_LEN_4 … #define MSCC_PHY_EXTENDED_INT … #define MSCC_PHY_EXTENDED_INT_MS_EGR … /* Extended Page 3 Registers */ #define MSCC_PHY_SERDES_TX_VALID_CNT … #define MSCC_PHY_SERDES_TX_CRC_ERR_CNT … #define MSCC_PHY_SERDES_RX_VALID_CNT … #define MSCC_PHY_SERDES_RX_CRC_ERR_CNT … /* Extended page GPIO Registers */ #define MSCC_DW8051_CNTL_STATUS … #define MICRO_NSOFT_RESET … #define RUN_FROM_INT_ROM … #define AUTOINC_ADDR … #define PATCH_RAM_CLK … #define MICRO_PATCH_EN … #define DW8051_CLK_EN … #define MICRO_CLK_EN … #define MICRO_CLK_DIVIDE(x) … #define MSCC_DW8051_VLD_MASK … /* x Address in range 1-4 */ #define MSCC_TRAP_ROM_ADDR(x) … #define MSCC_PATCH_RAM_ADDR(x) … #define MSCC_INT_MEM_ADDR … #define MSCC_INT_MEM_CNTL … #define READ_SFR … #define READ_PRAM … #define READ_ROM … #define READ_RAM … #define INT_MEM_WRITE_EN … #define EN_PATCH_RAM_TRAP_ADDR(x) … #define INT_MEM_DATA_M … #define INT_MEM_DATA(x) … #define MSCC_PHY_PROC_CMD … #define PROC_CMD_NCOMPLETED … #define PROC_CMD_FAILED … #define PROC_CMD_SGMII_PORT(x) … #define PROC_CMD_FIBER_PORT(x) … #define PROC_CMD_QSGMII_PORT … #define PROC_CMD_RST_CONF_PORT … #define PROC_CMD_RECONF_PORT … #define PROC_CMD_READ_MOD_WRITE_PORT … #define PROC_CMD_WRITE … #define PROC_CMD_READ … #define PROC_CMD_FIBER_DISABLE … #define PROC_CMD_FIBER_100BASE_FX … #define PROC_CMD_FIBER_1000BASE_X … #define PROC_CMD_SGMII_MAC … #define PROC_CMD_QSGMII_MAC … #define PROC_CMD_NO_MAC_CONF … #define PROC_CMD_1588_DEFAULT_INIT … #define PROC_CMD_NOP … #define PROC_CMD_PHY_INIT … #define PROC_CMD_CRC16 … #define PROC_CMD_FIBER_MEDIA_CONF … #define PROC_CMD_MCB_ACCESS_MAC_CONF … #define PROC_CMD_NCOMPLETED_TIMEOUT_MS … #define MSCC_PHY_MAC_CFG_FASTLINK … #define MAC_CFG_MASK … #define MAC_CFG_SGMII … #define MAC_CFG_QSGMII … #define MAC_CFG_RGMII … /* Test page Registers */ #define MSCC_PHY_TEST_PAGE_5 … #define MSCC_PHY_TEST_PAGE_8 … #define TR_CLK_DISABLE … #define MSCC_PHY_TEST_PAGE_9 … #define MSCC_PHY_TEST_PAGE_20 … #define MSCC_PHY_TEST_PAGE_24 … /* Token ring page Registers */ #define MSCC_PHY_TR_CNTL … #define TR_WRITE … #define TR_ADDR(x) … #define MSCC_PHY_TR_LSB … #define MSCC_PHY_TR_MSB … /* Microsemi PHY ID's * Code assumes lowest nibble is 0 */ #define PHY_ID_VSC8501 … #define PHY_ID_VSC8502 … #define PHY_ID_VSC8504 … #define PHY_ID_VSC8514 … #define PHY_ID_VSC8530 … #define PHY_ID_VSC8531 … #define PHY_ID_VSC8540 … #define PHY_ID_VSC8541 … #define PHY_ID_VSC8552 … #define PHY_ID_VSC856X … #define PHY_ID_VSC8572 … #define PHY_ID_VSC8574 … #define PHY_ID_VSC8575 … #define PHY_ID_VSC8582 … #define PHY_ID_VSC8584 … #define PHY_VENDOR_MSCC … #define MSCC_VDDMAC_1500 … #define MSCC_VDDMAC_1800 … #define MSCC_VDDMAC_2500 … #define MSCC_VDDMAC_3300 … #define DOWNSHIFT_COUNT_MAX … #define MAX_LEDS … #define VSC8584_SUPP_LED_MODES … #define VSC85XX_SUPP_LED_MODES … #define MSCC_VSC8584_REVB_INT8051_FW … #define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR … #define MSCC_VSC8584_REVB_INT8051_FW_CRC … #define MSCC_VSC8574_REVB_INT8051_FW … #define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR … #define MSCC_VSC8574_REVB_INT8051_FW_CRC … #define VSC8584_REVB … #define MSCC_DEV_REV_MASK … #define MSCC_ROM_TRAP_SERDES_6G_CFG … #define MSCC_RAM_TRAP_SERDES_6G_CFG … #define PATCH_VEC_ZERO_EN … struct reg_val { … }; struct vsc85xx_hw_stat { … }; struct vsc8531_private { … }; /* Shared structure between the PHYs of the same package. * gpio_lock: used for PHC operations. Common for all PHYs as the load/save GPIO * is shared. */ enum vsc85xx_global_phy { … }; struct vsc85xx_shared_private { … }; #if IS_ENABLED(CONFIG_OF_MDIO) struct vsc8531_edge_rate_table { … }; #endif /* CONFIG_OF_MDIO */ enum csr_target { … }; u32 vsc85xx_csr_read(struct phy_device *phydev, enum csr_target target, u32 reg); int vsc85xx_csr_write(struct phy_device *phydev, enum csr_target target, u32 reg, u32 val); int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val); int phy_base_read(struct phy_device *phydev, u32 regnum); int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb); int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb); int vsc8584_cmd(struct phy_device *phydev, u16 val); #if IS_ENABLED(CONFIG_MACSEC) int vsc8584_macsec_init(struct phy_device *phydev); void vsc8584_handle_macsec_interrupt(struct phy_device *phydev); void vsc8584_config_macsec_intr(struct phy_device *phydev); #else static inline int vsc8584_macsec_init(struct phy_device *phydev) { return 0; } static inline void vsc8584_handle_macsec_interrupt(struct phy_device *phydev) { } static inline void vsc8584_config_macsec_intr(struct phy_device *phydev) { } #endif #if IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING) void vsc85xx_link_change_notify(struct phy_device *phydev); void vsc8584_config_ts_intr(struct phy_device *phydev); int vsc8584_ptp_init(struct phy_device *phydev); int vsc8584_ptp_probe_once(struct phy_device *phydev); int vsc8584_ptp_probe(struct phy_device *phydev); irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev); #else static inline void vsc85xx_link_change_notify(struct phy_device *phydev) { } static inline void vsc8584_config_ts_intr(struct phy_device *phydev) { } static inline int vsc8584_ptp_init(struct phy_device *phydev) { return 0; } static inline int vsc8584_ptp_probe_once(struct phy_device *phydev) { return 0; } static inline int vsc8584_ptp_probe(struct phy_device *phydev) { return 0; } static inline irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev) { return IRQ_NONE; } #endif #endif /* _MSCC_PHY_H_ */
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