linux/drivers/net/phy/mscc/mscc_mac.h

/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
 * Driver for Microsemi VSC85xx PHYs
 *
 * Copyright (c) 2020 Microsemi Corporation
 */

#ifndef _MSCC_PHY_LINE_MAC_H_
#define _MSCC_PHY_LINE_MAC_H_

#define MSCC_MAC_CFG_ENA_CFG
#define MSCC_MAC_CFG_MODE_CFG
#define MSCC_MAC_CFG_MAXLEN_CFG
#define MSCC_MAC_CFG_NUM_TAGS_CFG
#define MSCC_MAC_CFG_TAGS_CFG
#define MSCC_MAC_CFG_ADV_CHK_CFG
#define MSCC_MAC_CFG_LFS_CFG
#define MSCC_MAC_CFG_LB_CFG
#define MSCC_MAC_CFG_PKTINF_CFG
#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL
#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2
#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL
#define MSCC_MAC_PAUSE_CFG_STATE
#define MSCC_MAC_PAUSE_CFG_MAC_ADDRESS_LSB
#define MSCC_MAC_PAUSE_CFG_MAC_ADDRESS_MSB
#define MSCC_MAC_STATUS_RX_LANE_STICKY_0
#define MSCC_MAC_STATUS_RX_LANE_STICKY_1
#define MSCC_MAC_STATUS_TX_MONITOR_STICKY
#define MSCC_MAC_STATUS_TX_MONITOR_STICKY_MASK
#define MSCC_MAC_STATUS_STICKY
#define MSCC_MAC_STATUS_STICKY_MASK
#define MSCC_MAC_STATS_32BIT_RX_HIH_CKSM_ERR_CNT
#define MSCC_MAC_STATS_32BIT_RX_XGMII_PROT_ERR_CNT
#define MSCC_MAC_STATS_32BIT_RX_SYMBOL_ERR_CNT
#define MSCC_MAC_STATS_32BIT_RX_PAUSE_CNT
#define MSCC_MAC_STATS_32BIT_RX_UNSUP_OPCODE_CNT
#define MSCC_MAC_STATS_32BIT_RX_UC_CNT
#define MSCC_MAC_STATS_32BIT_RX_MC_CNT
#define MSCC_MAC_STATS_32BIT_RX_BC_CNT
#define MSCC_MAC_STATS_32BIT_RX_CRC_ERR_CNT
#define MSCC_MAC_STATS_32BIT_RX_UNDERSIZE_CNT
#define MSCC_MAC_STATS_32BIT_RX_FRAGMENTS_CNT
#define MSCC_MAC_STATS_32BIT_RX_IN_RANGE_LEN_ERR_CNT
#define MSCC_MAC_STATS_32BIT_RX_OUT_OF_RANGE_LEN_ERR_CNT
#define MSCC_MAC_STATS_32BIT_RX_OVERSIZE_CNT
#define MSCC_MAC_STATS_32BIT_RX_JABBERS_CNT
#define MSCC_MAC_STATS_32BIT_RX_SIZE64_CNT
#define MSCC_MAC_STATS_32BIT_RX_SIZE65TO127_CNT
#define MSCC_MAC_STATS_32BIT_RX_SIZE128TO255_CNT
#define MSCC_MAC_STATS_32BIT_RX_SIZE256TO511_CNT
#define MSCC_MAC_STATS_32BIT_RX_SIZE512TO1023_CNT
#define MSCC_MAC_STATS_32BIT_RX_SIZE1024TO1518_CNT
#define MSCC_MAC_STATS_32BIT_RX_SIZE1519TOMAX_CNT
#define MSCC_MAC_STATS_32BIT_RX_IPG_SHRINK_CNT
#define MSCC_MAC_STATS_32BIT_TX_PAUSE_CNT
#define MSCC_MAC_STATS_32BIT_TX_UC_CNT
#define MSCC_MAC_STATS_32BIT_TX_MC_CNT
#define MSCC_MAC_STATS_32BIT_TX_BC_CNT
#define MSCC_MAC_STATS_32BIT_TX_SIZE64_CNT
#define MSCC_MAC_STATS_32BIT_TX_SIZE65TO127_CNT
#define MSCC_MAC_STATS_32BIT_TX_SIZE128TO255_CNT
#define MSCC_MAC_STATS_32BIT_TX_SIZE256TO511_CNT
#define MSCC_MAC_STATS_32BIT_TX_SIZE512TO1023_CNT
#define MSCC_MAC_STATS_32BIT_TX_SIZE1024TO1518_CNT
#define MSCC_MAC_STATS_32BIT_TX_SIZE1519TOMAX_CNT
#define MSCC_MAC_STATS_40BIT_RX_BAD_BYTES_CNT
#define MSCC_MAC_STATS_40BIT_RX_BAD_BYTES_MSB_CNT
#define MSCC_MAC_STATS_40BIT_RX_OK_BYTES_CNT
#define MSCC_MAC_STATS_40BIT_RX_OK_BYTES_MSB_CNT
#define MSCC_MAC_STATS_40BIT_RX_IN_BYTES_CNT
#define MSCC_MAC_STATS_40BIT_RX_IN_BYTES_MSB_CNT
#define MSCC_MAC_STATS_40BIT_TX_OK_BYTES_CNT
#define MSCC_MAC_STATS_40BIT_TX_OK_BYTES_MSB_CNT
#define MSCC_MAC_STATS_40BIT_TX_OUT_BYTES_CNT
#define MSCC_MAC_STATS_40BIT_TX_OUT_BYTES_MSB_CNT

#define MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA
#define MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA
#define MSCC_MAC_CFG_ENA_CFG_RX_SW_RST
#define MSCC_MAC_CFG_ENA_CFG_TX_SW_RST
#define MSCC_MAC_CFG_ENA_CFG_RX_ENA
#define MSCC_MAC_CFG_ENA_CFG_TX_ENA

#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL(x)
#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL_M
#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE
#define MSCC_MAC_CFG_MODE_CFG_TUNNEL_PAUSE_FRAMES
#define MSCC_MAC_CFG_MODE_CFG_MAC_PREAMBLE_CFG(x)
#define MSCC_MAC_CFG_MODE_CFG_MAC_PREAMBLE_CFG_M
#define MSCC_MAC_CFG_MODE_CFG_MAC_IPG_CFG
#define MSCC_MAC_CFG_MODE_CFG_XGMII_GEN_MODE_ENA
#define MSCC_MAC_CFG_MODE_CFG_HIH_CRC_CHECK
#define MSCC_MAC_CFG_MODE_CFG_UNDERSIZED_FRAME_DROP_DIS
#define MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC

#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_TAG_CHK
#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN(x)
#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_M

#define MSCC_MAC_CFG_TAGS_CFG_RSZ
#define MSCC_MAC_CFG_TAGS_CFG_TAG_ID(x)
#define MSCC_MAC_CFG_TAGS_CFG_TAG_ID_M
#define MSCC_MAC_CFG_TAGS_CFG_TAG_ENA

#define MSCC_MAC_CFG_ADV_CHK_CFG_EXT_EOP_CHK_ENA
#define MSCC_MAC_CFG_ADV_CHK_CFG_EXT_SOP_CHK_ENA
#define MSCC_MAC_CFG_ADV_CHK_CFG_SFD_CHK_ENA
#define MSCC_MAC_CFG_ADV_CHK_CFG_PRM_SHK_CHK_DIS
#define MSCC_MAC_CFG_ADV_CHK_CFG_PRM_CHK_ENA
#define MSCC_MAC_CFG_ADV_CHK_CFG_OOR_ERR_ENA
#define MSCC_MAC_CFG_ADV_CHK_CFG_INR_ERR_ENA

#define MSCC_MAC_CFG_LFS_CFG_LFS_INH_TX
#define MSCC_MAC_CFG_LFS_CFG_LFS_DIS_TX
#define MSCC_MAC_CFG_LFS_CFG_LFS_UNIDIR_ENA
#define MSCC_MAC_CFG_LFS_CFG_USE_LEADING_EDGE_DETECT
#define MSCC_MAC_CFG_LFS_CFG_SPURIOUS_Q_DIS
#define MSCC_MAC_CFG_LFS_CFG_LFS_MODE_ENA

#define MSCC_MAC_CFG_LB_CFG_XGMII_HOST_LB_ENA
#define MSCC_MAC_CFG_LB_CFG_XGMII_PHY_LB_ENA

#define MSCC_MAC_CFG_PKTINF_CFG_STRIP_FCS_ENA
#define MSCC_MAC_CFG_PKTINF_CFG_INSERT_FCS_ENA
#define MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA
#define MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA
#define MSCC_MAC_CFG_PKTINF_CFG_LPI_RELAY_ENA
#define MSCC_MAC_CFG_PKTINF_CFG_LF_RELAY_ENA
#define MSCC_MAC_CFG_PKTINF_CFG_RF_RELAY_ENA
#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING
#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_RX_PADDING
#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_4BYTE_PREAMBLE
#define MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS(x)
#define MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS_M

#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE(x)
#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE_M
#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_WAIT_FOR_LPI_LOW
#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_USE_PAUSE_STALL_ENA
#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_REPL_MODE
#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_FRC_FRAME
#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE(x)
#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE_M

#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_EARLY_PAUSE_DETECT_ENA
#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PRE_CRC_MODE
#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_TIMER_ENA
#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_REACT_ENA
#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA
#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_MODE

#define MSCC_MAC_PAUSE_CFG_STATE_PAUSE_STATE
#define MSCC_MAC_PAUSE_CFG_STATE_MAC_TX_PAUSE_GEN

#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL
#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(x)
#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M

#endif /* _MSCC_PHY_LINE_MAC_H_ */