/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ /* * Device Tree constants for the Texas Instruments DP83867 PHY * * Author: Dan Murphy <[email protected]> * * Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef _DT_BINDINGS_TI_DP83867_H #define _DT_BINDINGS_TI_DP83867_H /* PHY CTRL bits */ #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB … #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB … #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB … #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB … /* RGMIIDCTL internal delay for rx and tx */ #define DP83867_RGMIIDCTL_250_PS … #define DP83867_RGMIIDCTL_500_PS … #define DP83867_RGMIIDCTL_750_PS … #define DP83867_RGMIIDCTL_1_NS … #define DP83867_RGMIIDCTL_1_25_NS … #define DP83867_RGMIIDCTL_1_50_NS … #define DP83867_RGMIIDCTL_1_75_NS … #define DP83867_RGMIIDCTL_2_00_NS … #define DP83867_RGMIIDCTL_2_25_NS … #define DP83867_RGMIIDCTL_2_50_NS … #define DP83867_RGMIIDCTL_2_75_NS … #define DP83867_RGMIIDCTL_3_00_NS … #define DP83867_RGMIIDCTL_3_25_NS … #define DP83867_RGMIIDCTL_3_50_NS … #define DP83867_RGMIIDCTL_3_75_NS … #define DP83867_RGMIIDCTL_4_00_NS … /* IO_MUX_CFG - Clock output selection */ #define DP83867_CLK_O_SEL_CHN_A_RCLK … #define DP83867_CLK_O_SEL_CHN_B_RCLK … #define DP83867_CLK_O_SEL_CHN_C_RCLK … #define DP83867_CLK_O_SEL_CHN_D_RCLK … #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 … #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 … #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 … #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 … #define DP83867_CLK_O_SEL_CHN_A_TCLK … #define DP83867_CLK_O_SEL_CHN_B_TCLK … #define DP83867_CLK_O_SEL_CHN_C_TCLK … #define DP83867_CLK_O_SEL_CHN_D_TCLK … #define DP83867_CLK_O_SEL_REF_CLK … /* Special flag to indicate clock should be off */ #define DP83867_CLK_O_SEL_OFF … #endif
Codebase Browser
linux