// SPDX-License-Identifier: GPL-2.0 /* Driver for the Texas Instruments DP83867 PHY * * Copyright (C) 2015 Texas Instruments Inc. */ #include <linux/ethtool.h> #include <linux/kernel.h> #include <linux/mii.h> #include <linux/module.h> #include <linux/of.h> #include <linux/phy.h> #include <linux/delay.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/bitfield.h> #include <linux/nvmem-consumer.h> #include <dt-bindings/net/ti-dp83867.h> #define DP83867_PHY_ID … #define DP83867_DEVADDR … #define MII_DP83867_PHYCTRL … #define MII_DP83867_PHYSTS … #define MII_DP83867_MICR … #define MII_DP83867_ISR … #define DP83867_CFG2 … #define DP83867_LEDCR1 … #define DP83867_LEDCR2 … #define DP83867_CFG3 … #define DP83867_CTRL … /* Extended Registers */ #define DP83867_FLD_THR_CFG … #define DP83867_CFG4 … #define DP83867_CFG4_SGMII_ANEG_MASK … #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS … #define DP83867_CFG4_SGMII_ANEG_TIMER_800US … #define DP83867_CFG4_SGMII_ANEG_TIMER_2US … #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS … #define DP83867_RGMIICTL … #define DP83867_STRAP_STS1 … #define DP83867_STRAP_STS2 … #define DP83867_RGMIIDCTL … #define DP83867_DSP_FFE_CFG … #define DP83867_RXFCFG … #define DP83867_RXFPMD1 … #define DP83867_RXFPMD2 … #define DP83867_RXFPMD3 … #define DP83867_RXFSOP1 … #define DP83867_RXFSOP2 … #define DP83867_RXFSOP3 … #define DP83867_IO_MUX_CFG … #define DP83867_SGMIICTL … #define DP83867_10M_SGMII_CFG … #define DP83867_10M_SGMII_RATE_ADAPT_MASK … #define DP83867_SW_RESET … #define DP83867_SW_RESTART … /* MICR Interrupt bits */ #define MII_DP83867_MICR_AN_ERR_INT_EN … #define MII_DP83867_MICR_SPEED_CHNG_INT_EN … #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN … #define MII_DP83867_MICR_PAGE_RXD_INT_EN … #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN … #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN … #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN … #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN … #define MII_DP83867_MICR_WOL_INT_EN … #define MII_DP83867_MICR_XGMII_ERR_INT_EN … #define MII_DP83867_MICR_POL_CHNG_INT_EN … #define MII_DP83867_MICR_JABBER_INT_EN … /* RGMIICTL bits */ #define DP83867_RGMII_TX_CLK_DELAY_EN … #define DP83867_RGMII_RX_CLK_DELAY_EN … /* SGMIICTL bits */ #define DP83867_SGMII_TYPE … /* RXFCFG bits*/ #define DP83867_WOL_MAGIC_EN … #define DP83867_WOL_BCAST_EN … #define DP83867_WOL_UCAST_EN … #define DP83867_WOL_SEC_EN … #define DP83867_WOL_ENH_MAC … /* STRAP_STS1 bits */ #define DP83867_STRAP_STS1_RESERVED … /* STRAP_STS2 bits */ #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK … #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT … #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK … #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT … #define DP83867_STRAP_STS2_CLK_SKEW_NONE … #define DP83867_STRAP_STS2_STRAP_FLD … /* PHY CTRL bits */ #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT … #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT … #define DP83867_PHYCR_FIFO_DEPTH_MAX … #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK … #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK … #define DP83867_PHYCR_RESERVED_MASK … #define DP83867_PHYCR_FORCE_LINK_GOOD … /* RGMIIDCTL bits */ #define DP83867_RGMII_TX_CLK_DELAY_MAX … #define DP83867_RGMII_TX_CLK_DELAY_SHIFT … #define DP83867_RGMII_TX_CLK_DELAY_INV … #define DP83867_RGMII_RX_CLK_DELAY_MAX … #define DP83867_RGMII_RX_CLK_DELAY_SHIFT … #define DP83867_RGMII_RX_CLK_DELAY_INV … /* IO_MUX_CFG bits */ #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK … #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX … #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN … #define DP83867_IO_MUX_CFG_CLK_O_DISABLE … #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK … #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT … /* PHY STS bits */ #define DP83867_PHYSTS_1000 … #define DP83867_PHYSTS_100 … #define DP83867_PHYSTS_DUPLEX … #define DP83867_PHYSTS_LINK … /* CFG2 bits */ #define DP83867_DOWNSHIFT_EN … #define DP83867_DOWNSHIFT_ATTEMPT_MASK … #define DP83867_DOWNSHIFT_1_COUNT_VAL … #define DP83867_DOWNSHIFT_2_COUNT_VAL … #define DP83867_DOWNSHIFT_4_COUNT_VAL … #define DP83867_DOWNSHIFT_8_COUNT_VAL … #define DP83867_DOWNSHIFT_1_COUNT … #define DP83867_DOWNSHIFT_2_COUNT … #define DP83867_DOWNSHIFT_4_COUNT … #define DP83867_DOWNSHIFT_8_COUNT … #define DP83867_SGMII_AUTONEG_EN … /* CFG3 bits */ #define DP83867_CFG3_INT_OE … #define DP83867_CFG3_ROBUST_AUTO_MDIX … /* CFG4 bits */ #define DP83867_CFG4_PORT_MIRROR_EN … /* FLD_THR_CFG */ #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK … #define DP83867_LED_COUNT … /* LED_DRV bits */ #define DP83867_LED_DRV_EN(x) … #define DP83867_LED_DRV_VAL(x) … #define DP83867_LED_POLARITY(x) … #define DP83867_LED_FN(idx, val) … #define DP83867_LED_FN_MASK(idx) … #define DP83867_LED_FN_RX_ERR … #define DP83867_LED_FN_RX_TX_ERR … #define DP83867_LED_FN_LINK_RX_TX … #define DP83867_LED_FN_FULL_DUPLEX … #define DP83867_LED_FN_LINK_100_1000_BT … #define DP83867_LED_FN_LINK_10_100_BT … #define DP83867_LED_FN_LINK_10_BT … #define DP83867_LED_FN_LINK_100_BTX … #define DP83867_LED_FN_LINK_1000_BT … #define DP83867_LED_FN_COLLISION … #define DP83867_LED_FN_RX … #define DP83867_LED_FN_TX … #define DP83867_LED_FN_RX_TX … #define DP83867_LED_FN_LINK … enum { … }; struct dp83867_private { … }; static int dp83867_ack_interrupt(struct phy_device *phydev) { … } static int dp83867_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) { … } static void dp83867_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) { … } static int dp83867_config_intr(struct phy_device *phydev) { … } static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev) { … } static int dp83867_read_status(struct phy_device *phydev) { … } static int dp83867_get_downshift(struct phy_device *phydev, u8 *data) { … } static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt) { … } static int dp83867_get_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, void *data) { … } static int dp83867_set_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, const void *data) { … } static int dp83867_config_port_mirroring(struct phy_device *phydev) { … } static int dp83867_verify_rgmii_cfg(struct phy_device *phydev) { … } #if IS_ENABLED(CONFIG_OF_MDIO) static int dp83867_of_init_io_impedance(struct phy_device *phydev) { … } static int dp83867_of_init(struct phy_device *phydev) { … } #else static int dp83867_of_init(struct phy_device *phydev) { struct dp83867_private *dp83867 = phydev->priv; u16 delay; /* For non-OF device, the RX and TX ID values are either strapped * or take from default value. So, we init RX & TX ID values here * so that the RGMIIDCTL is configured correctly later in * dp83867_config_init(); */ delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL); dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX; dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) & DP83867_RGMII_TX_CLK_DELAY_MAX; /* Per datasheet, IO impedance is default to 50-ohm, so we set the * same here or else the default '0' means highest IO impedance * which is wrong. */ dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2; /* For non-OF device, the RX and TX FIFO depths are taken from * default value. So, we init RX & TX FIFO depths here * so that it is configured correctly later in dp83867_config_init(); */ dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; return 0; } #endif /* CONFIG_OF_MDIO */ static int dp83867_suspend(struct phy_device *phydev) { … } static int dp83867_resume(struct phy_device *phydev) { … } static int dp83867_probe(struct phy_device *phydev) { … } static int dp83867_config_init(struct phy_device *phydev) { … } static int dp83867_phy_reset(struct phy_device *phydev) { … } static void dp83867_link_change_notify(struct phy_device *phydev) { … } static int dp83867_loopback(struct phy_device *phydev, bool enable) { … } static int dp83867_led_brightness_set(struct phy_device *phydev, u8 index, enum led_brightness brightness) { … } static int dp83867_led_mode(u8 index, unsigned long rules) { … } static int dp83867_led_hw_is_supported(struct phy_device *phydev, u8 index, unsigned long rules) { … } static int dp83867_led_hw_control_set(struct phy_device *phydev, u8 index, unsigned long rules) { … } static int dp83867_led_hw_control_get(struct phy_device *phydev, u8 index, unsigned long *rules) { … } static int dp83867_led_polarity_set(struct phy_device *phydev, int index, unsigned long modes) { … } static struct phy_driver dp83867_driver[] = …; module_phy_driver(dp83867_driver); static struct mdio_device_id __maybe_unused dp83867_tbl[] = …; MODULE_DEVICE_TABLE(mdio, dp83867_tbl); MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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