// SPDX-License-Identifier: GPL-2.0 /* Driver for the Texas Instruments DP83869 PHY * Copyright (C) 2019 Texas Instruments Inc. */ #include <linux/ethtool.h> #include <linux/etherdevice.h> #include <linux/kernel.h> #include <linux/mii.h> #include <linux/module.h> #include <linux/of.h> #include <linux/phy.h> #include <linux/delay.h> #include <linux/bitfield.h> #include <dt-bindings/net/ti-dp83869.h> #define DP83869_PHY_ID … #define DP83561_PHY_ID … #define DP83869_DEVADDR … #define MII_DP83869_PHYCTRL … #define MII_DP83869_MICR … #define MII_DP83869_ISR … #define DP83869_CFG2 … #define DP83869_CTRL … #define DP83869_CFG4 … /* Extended Registers */ #define DP83869_GEN_CFG3 … #define DP83869_RGMIICTL … #define DP83869_STRAP_STS1 … #define DP83869_RGMIIDCTL … #define DP83869_RXFCFG … #define DP83869_RXFPMD1 … #define DP83869_RXFPMD2 … #define DP83869_RXFPMD3 … #define DP83869_RXFSOP1 … #define DP83869_RXFSOP2 … #define DP83869_RXFSOP3 … #define DP83869_IO_MUX_CFG … #define DP83869_OP_MODE … #define DP83869_FX_CTRL … #define DP83869_SW_RESET … #define DP83869_SW_RESTART … /* MICR Interrupt bits */ #define MII_DP83869_MICR_AN_ERR_INT_EN … #define MII_DP83869_MICR_SPEED_CHNG_INT_EN … #define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN … #define MII_DP83869_MICR_PAGE_RXD_INT_EN … #define MII_DP83869_MICR_AUTONEG_COMP_INT_EN … #define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN … #define MII_DP83869_MICR_FALSE_CARRIER_INT_EN … #define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN … #define MII_DP83869_MICR_WOL_INT_EN … #define MII_DP83869_MICR_XGMII_ERR_INT_EN … #define MII_DP83869_MICR_POL_CHNG_INT_EN … #define MII_DP83869_MICR_JABBER_INT_EN … #define MII_DP83869_BMCR_DEFAULT … #define MII_DP83869_FIBER_ADVERTISE … /* This is the same bit mask as the BMCR so re-use the BMCR default */ #define DP83869_FX_CTRL_DEFAULT … /* CFG1 bits */ #define DP83869_CFG1_DEFAULT … /* RGMIICTL bits */ #define DP83869_RGMII_TX_CLK_DELAY_EN … #define DP83869_RGMII_RX_CLK_DELAY_EN … /* RGMIIDCTL */ #define DP83869_RGMII_CLK_DELAY_SHIFT … #define DP83869_CLK_DELAY_DEF … /* STRAP_STS1 bits */ #define DP83869_STRAP_OP_MODE_MASK … #define DP83869_STRAP_STS1_RESERVED … #define DP83869_STRAP_MIRROR_ENABLED … /* PHYCTRL bits */ #define DP83869_RX_FIFO_SHIFT … #define DP83869_TX_FIFO_SHIFT … /* PHY_CTRL lower bytes 0x48 are declared as reserved */ #define DP83869_PHY_CTRL_DEFAULT … #define DP83869_PHYCR_FIFO_DEPTH_MASK … #define DP83869_PHYCR_RESERVED_MASK … /* IO_MUX_CFG bits */ #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL … #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX … #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN … #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK … #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT … /* CFG3 bits */ #define DP83869_CFG3_PORT_MIRROR_EN … /* CFG4 bits */ #define DP83869_INT_OE … /* OP MODE */ #define DP83869_OP_MODE_MII … #define DP83869_SGMII_RGMII_BRIDGE … /* RXFCFG bits*/ #define DP83869_WOL_MAGIC_EN … #define DP83869_WOL_PATTERN_EN … #define DP83869_WOL_BCAST_EN … #define DP83869_WOL_UCAST_EN … #define DP83869_WOL_SEC_EN … #define DP83869_WOL_ENH_MAC … /* CFG2 bits */ #define DP83869_DOWNSHIFT_EN … #define DP83869_DOWNSHIFT_ATTEMPT_MASK … #define DP83869_DOWNSHIFT_1_COUNT_VAL … #define DP83869_DOWNSHIFT_2_COUNT_VAL … #define DP83869_DOWNSHIFT_4_COUNT_VAL … #define DP83869_DOWNSHIFT_8_COUNT_VAL … #define DP83869_DOWNSHIFT_1_COUNT … #define DP83869_DOWNSHIFT_2_COUNT … #define DP83869_DOWNSHIFT_4_COUNT … #define DP83869_DOWNSHIFT_8_COUNT … enum { … }; struct dp83869_private { … }; static int dp83869_read_status(struct phy_device *phydev) { … } static int dp83869_ack_interrupt(struct phy_device *phydev) { … } static int dp83869_config_intr(struct phy_device *phydev) { … } static irqreturn_t dp83869_handle_interrupt(struct phy_device *phydev) { … } static int dp83869_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) { … } static void dp83869_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) { … } static int dp83869_get_downshift(struct phy_device *phydev, u8 *data) { … } static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt) { … } static int dp83869_get_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, void *data) { … } static int dp83869_set_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, const void *data) { … } static int dp83869_config_port_mirroring(struct phy_device *phydev) { … } static int dp83869_set_strapped_mode(struct phy_device *phydev) { … } #if IS_ENABLED(CONFIG_OF_MDIO) static const int dp83869_internal_delay[] = …; static int dp83869_of_init(struct phy_device *phydev) { … } #else static int dp83869_of_init(struct phy_device *phydev) { return dp83869_set_strapped_mode(phydev); } #endif /* CONFIG_OF_MDIO */ static int dp83869_configure_rgmii(struct phy_device *phydev, struct dp83869_private *dp83869) { … } static int dp83869_configure_fiber(struct phy_device *phydev, struct dp83869_private *dp83869) { … } static int dp83869_configure_mode(struct phy_device *phydev, struct dp83869_private *dp83869) { … } static int dp83869_config_init(struct phy_device *phydev) { … } static int dp83869_probe(struct phy_device *phydev) { … } static int dp83869_phy_reset(struct phy_device *phydev) { … } #define DP83869_PHY_DRIVER(_id, _name) … static struct phy_driver dp83869_driver[] = …; module_phy_driver(dp83869_driver); static struct mdio_device_id __maybe_unused dp83869_tbl[] = …; MODULE_DEVICE_TABLE(mdio, dp83869_tbl); MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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