// SPDX-License-Identifier: GPL-2.0 // Copyright (C) 2018 Microchip Technology #include <linux/kernel.h> #include <linux/module.h> #include <linux/delay.h> #include <linux/mii.h> #include <linux/phy.h> #include <linux/ethtool.h> #include <linux/ethtool_netlink.h> #include <linux/bitfield.h> #define PHY_ID_LAN87XX … #define PHY_ID_LAN937X … /* External Register Control Register */ #define LAN87XX_EXT_REG_CTL … #define LAN87XX_EXT_REG_CTL_RD_CTL … #define LAN87XX_EXT_REG_CTL_WR_CTL … #define LAN87XX_REG_BANK_SEL_MASK … #define LAN87XX_REG_ADDR_MASK … /* External Register Read Data Register */ #define LAN87XX_EXT_REG_RD_DATA … /* External Register Write Data Register */ #define LAN87XX_EXT_REG_WR_DATA … /* Interrupt Source Register */ #define LAN87XX_INTERRUPT_SOURCE … #define LAN87XX_INTERRUPT_SOURCE_2 … /* Interrupt Mask Register */ #define LAN87XX_INTERRUPT_MASK … #define LAN87XX_MASK_LINK_UP … #define LAN87XX_MASK_LINK_DOWN … #define LAN87XX_INTERRUPT_MASK_2 … #define LAN87XX_MASK_COMM_RDY … /* MISC Control 1 Register */ #define LAN87XX_CTRL_1 … #define LAN87XX_MASK_RGMII_TXC_DLY_EN … #define LAN87XX_MASK_RGMII_RXC_DLY_EN … /* phyaccess nested types */ #define PHYACC_ATTR_MODE_READ … #define PHYACC_ATTR_MODE_WRITE … #define PHYACC_ATTR_MODE_MODIFY … #define PHYACC_ATTR_MODE_POLL … #define PHYACC_ATTR_BANK_SMI … #define PHYACC_ATTR_BANK_MISC … #define PHYACC_ATTR_BANK_PCS … #define PHYACC_ATTR_BANK_AFE … #define PHYACC_ATTR_BANK_DSP … #define PHYACC_ATTR_BANK_MAX … /* measurement defines */ #define LAN87XX_CABLE_TEST_OK … #define LAN87XX_CABLE_TEST_OPEN … #define LAN87XX_CABLE_TEST_SAME_SHORT … /* T1 Registers */ #define T1_AFE_PORT_CFG1_REG … #define T1_POWER_DOWN_CONTROL_REG … #define T1_SLV_FD_MULT_CFG_REG … #define T1_CDR_CFG_PRE_LOCK_REG … #define T1_CDR_CFG_POST_LOCK_REG … #define T1_LCK_STG2_MUFACT_CFG_REG … #define T1_LCK_STG3_MUFACT_CFG_REG … #define T1_POST_LCK_MUFACT_CFG_REG … #define T1_TX_RX_FIFO_CFG_REG … #define T1_TX_LPF_FIR_CFG_REG … #define T1_COEF_CLK_PWR_DN_CFG … #define T1_COEF_RW_CTL_CFG … #define T1_SQI_CONFIG_REG … #define T1_SQI_CONFIG2_REG … #define T1_DCQ_SQI_REG … #define T1_DCQ_SQI_MSK … #define T1_MDIO_CONTROL2_REG … #define T1_INTERRUPT_SOURCE_REG … #define T1_INTERRUPT2_SOURCE_REG … #define T1_EQ_FD_STG1_FRZ_CFG … #define T1_EQ_FD_STG2_FRZ_CFG … #define T1_EQ_FD_STG3_FRZ_CFG … #define T1_EQ_FD_STG4_FRZ_CFG … #define T1_EQ_WT_FD_LCK_FRZ_CFG … #define T1_PST_EQ_LCK_STG1_FRZ_CFG … #define T1_MODE_STAT_REG … #define T1_LINK_UP_MSK … /* SQI defines */ #define LAN87XX_MAX_SQI … #define DRIVER_AUTHOR … #define DRIVER_DESC … struct access_ereg_val { … }; static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank) { … } static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank, u8 offset, u16 val) { … } static int access_ereg_modify_changed(struct phy_device *phydev, u8 bank, u8 offset, u16 val, u16 mask) { … } static int access_smi_poll_timeout(struct phy_device *phydev, u8 offset, u16 mask, u16 clr) { … } static int lan87xx_config_rgmii_delay(struct phy_device *phydev) { … } static int lan87xx_phy_init_cmd(struct phy_device *phydev, const struct access_ereg_val *cmd_seq, int cnt) { … } static int lan87xx_phy_init(struct phy_device *phydev) { … } static int lan87xx_phy_config_intr(struct phy_device *phydev) { … } static irqreturn_t lan87xx_handle_interrupt(struct phy_device *phydev) { … } static int lan87xx_config_init(struct phy_device *phydev) { … } static int microchip_cable_test_start_common(struct phy_device *phydev) { … } static int lan87xx_cable_test_start(struct phy_device *phydev) { … } static int lan87xx_cable_test_report_trans(u32 result) { … } static int lan87xx_cable_test_report(struct phy_device *phydev) { … } static int lan87xx_cable_test_get_status(struct phy_device *phydev, bool *finished) { … } static int lan87xx_read_status(struct phy_device *phydev) { … } static int lan87xx_config_aneg(struct phy_device *phydev) { … } static int lan87xx_get_sqi(struct phy_device *phydev) { … } static int lan87xx_get_sqi_max(struct phy_device *phydev) { … } static struct phy_driver microchip_t1_phy_driver[] = …; module_phy_driver(microchip_t1_phy_driver); static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = …; MODULE_DEVICE_TABLE(mdio, microchip_t1_tbl); MODULE_AUTHOR(…); MODULE_DESCRIPTION(…); MODULE_LICENSE(…) …;
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