/* SPDX-License-Identifier: GPL-2.0+ */ /* Applied Micro X-Gene SoC MDIO Driver * * Copyright (c) 2016, Applied Micro Circuits Corporation * Author: Iyappan Subramanian <[email protected]> */ #ifndef __MDIO_XGENE_H__ #define __MDIO_XGENE_H__ #include <linux/bits.h> #include <linux/spinlock.h> #include <linux/types.h> #define BLOCK_XG_MDIO_CSR_OFFSET … #define BLOCK_DIAG_CSR_OFFSET … #define XGENET_CONFIG_REG_ADDR … #define MAC_ADDR_REG_OFFSET … #define MAC_COMMAND_REG_OFFSET … #define MAC_WRITE_REG_OFFSET … #define MAC_READ_REG_OFFSET … #define MAC_COMMAND_DONE_REG_OFFSET … #define CLKEN_OFFSET … #define SRST_OFFSET … #define MENET_CFG_MEM_RAM_SHUTDOWN_ADDR … #define MENET_BLOCK_MEM_RDY_ADDR … #define MAC_CONFIG_1_ADDR … #define MII_MGMT_COMMAND_ADDR … #define MII_MGMT_ADDRESS_ADDR … #define MII_MGMT_CONTROL_ADDR … #define MII_MGMT_STATUS_ADDR … #define MII_MGMT_INDICATORS_ADDR … #define SOFT_RESET … #define MII_MGMT_CONFIG_ADDR … #define MII_MGMT_COMMAND_ADDR … #define MII_MGMT_ADDRESS_ADDR … #define MII_MGMT_CONTROL_ADDR … #define MII_MGMT_STATUS_ADDR … #define MII_MGMT_INDICATORS_ADDR … #define MIIM_COMMAND_ADDR … #define MIIM_FIELD_ADDR … #define MIIM_CONFIGURATION_ADDR … #define MIIM_LINKFAILVECTOR_ADDR … #define MIIM_INDICATOR_ADDR … #define MIIMRD_FIELD_ADDR … #define MDIO_CSR_OFFSET … #define REG_ADDR_POS … #define REG_ADDR_LEN … #define PHY_ADDR_POS … #define PHY_ADDR_LEN … #define HSTMIIMWRDAT_POS … #define HSTMIIMWRDAT_LEN … #define HSTPHYADX_POS … #define HSTPHYADX_LEN … #define HSTREGADX_POS … #define HSTREGADX_LEN … #define HSTLDCMD … #define HSTMIIMCMD_POS … #define HSTMIIMCMD_LEN … #define BUSY_MASK … #define READ_CYCLE_MASK … enum xgene_enet_cmd { … }; enum { … }; enum xgene_mdio_id { … }; struct xgene_mdio_pdata { … }; /* Set the specified value into a bit-field defined by its starting position * and length within a single u64. */ static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val) { … } #define SET_VAL(field, val) … #define SET_BIT(field) … /* Get the value from a bit-field defined by its starting position * and length within the specified u64. */ static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src) { … } #define GET_VAL(field, src) … #define GET_BIT(field, src) … u32 xgene_mdio_rd_mac(struct xgene_mdio_pdata *pdata, u32 rd_addr); void xgene_mdio_wr_mac(struct xgene_mdio_pdata *pdata, u32 wr_addr, u32 data); int xgene_mdio_rgmii_read(struct mii_bus *bus, int phy_id, int reg); int xgene_mdio_rgmii_write(struct mii_bus *bus, int phy_id, int reg, u16 data); struct phy_device *xgene_enet_phy_register(struct mii_bus *bus, int phy_addr); #endif /* __MDIO_XGENE_H__ */
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