/* SPDX-License-Identifier: GPL-2.0 * * mcp251xfd - Microchip MCP251xFD Family CAN controller driver * * Copyright (c) 2019, 2020, 2021, 2023 Pengutronix, * Marc Kleine-Budde <[email protected]> * Copyright (c) 2019 Martin Sperl <[email protected]> */ #ifndef _MCP251XFD_H #define _MCP251XFD_H #include <linux/bitfield.h> #include <linux/can/core.h> #include <linux/can/dev.h> #include <linux/can/rx-offload.h> #include <linux/gpio/consumer.h> #include <linux/kernel.h> #include <linux/netdevice.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/spi/spi.h> #include <linux/timecounter.h> #include <linux/workqueue.h> /* MPC251x registers */ /* CAN FD Controller Module SFR */ #define MCP251XFD_REG_CON … #define MCP251XFD_REG_CON_TXBWS_MASK … #define MCP251XFD_REG_CON_ABAT … #define MCP251XFD_REG_CON_REQOP_MASK … #define MCP251XFD_REG_CON_MODE_MIXED … #define MCP251XFD_REG_CON_MODE_SLEEP … #define MCP251XFD_REG_CON_MODE_INT_LOOPBACK … #define MCP251XFD_REG_CON_MODE_LISTENONLY … #define MCP251XFD_REG_CON_MODE_CONFIG … #define MCP251XFD_REG_CON_MODE_EXT_LOOPBACK … #define MCP251XFD_REG_CON_MODE_CAN2_0 … #define MCP251XFD_REG_CON_MODE_RESTRICTED … #define MCP251XFD_REG_CON_OPMOD_MASK … #define MCP251XFD_REG_CON_TXQEN … #define MCP251XFD_REG_CON_STEF … #define MCP251XFD_REG_CON_SERR2LOM … #define MCP251XFD_REG_CON_ESIGM … #define MCP251XFD_REG_CON_RTXAT … #define MCP251XFD_REG_CON_BRSDIS … #define MCP251XFD_REG_CON_BUSY … #define MCP251XFD_REG_CON_WFT_MASK … #define MCP251XFD_REG_CON_WFT_T00FILTER … #define MCP251XFD_REG_CON_WFT_T01FILTER … #define MCP251XFD_REG_CON_WFT_T10FILTER … #define MCP251XFD_REG_CON_WFT_T11FILTER … #define MCP251XFD_REG_CON_WAKFIL … #define MCP251XFD_REG_CON_PXEDIS … #define MCP251XFD_REG_CON_ISOCRCEN … #define MCP251XFD_REG_CON_DNCNT_MASK … #define MCP251XFD_REG_NBTCFG … #define MCP251XFD_REG_NBTCFG_BRP_MASK … #define MCP251XFD_REG_NBTCFG_TSEG1_MASK … #define MCP251XFD_REG_NBTCFG_TSEG2_MASK … #define MCP251XFD_REG_NBTCFG_SJW_MASK … #define MCP251XFD_REG_DBTCFG … #define MCP251XFD_REG_DBTCFG_BRP_MASK … #define MCP251XFD_REG_DBTCFG_TSEG1_MASK … #define MCP251XFD_REG_DBTCFG_TSEG2_MASK … #define MCP251XFD_REG_DBTCFG_SJW_MASK … #define MCP251XFD_REG_TDC … #define MCP251XFD_REG_TDC_EDGFLTEN … #define MCP251XFD_REG_TDC_SID11EN … #define MCP251XFD_REG_TDC_TDCMOD_MASK … #define MCP251XFD_REG_TDC_TDCMOD_AUTO … #define MCP251XFD_REG_TDC_TDCMOD_MANUAL … #define MCP251XFD_REG_TDC_TDCMOD_DISABLED … #define MCP251XFD_REG_TDC_TDCO_MASK … #define MCP251XFD_REG_TDC_TDCV_MASK … #define MCP251XFD_REG_TBC … #define MCP251XFD_REG_TSCON … #define MCP251XFD_REG_TSCON_TSRES … #define MCP251XFD_REG_TSCON_TSEOF … #define MCP251XFD_REG_TSCON_TBCEN … #define MCP251XFD_REG_TSCON_TBCPRE_MASK … #define MCP251XFD_REG_VEC … #define MCP251XFD_REG_VEC_RXCODE_MASK … #define MCP251XFD_REG_VEC_TXCODE_MASK … #define MCP251XFD_REG_VEC_FILHIT_MASK … #define MCP251XFD_REG_VEC_ICODE_MASK … #define MCP251XFD_REG_INT … #define MCP251XFD_REG_INT_IF_MASK … #define MCP251XFD_REG_INT_IE_MASK … #define MCP251XFD_REG_INT_IVMIE … #define MCP251XFD_REG_INT_WAKIE … #define MCP251XFD_REG_INT_CERRIE … #define MCP251XFD_REG_INT_SERRIE … #define MCP251XFD_REG_INT_RXOVIE … #define MCP251XFD_REG_INT_TXATIE … #define MCP251XFD_REG_INT_SPICRCIE … #define MCP251XFD_REG_INT_ECCIE … #define MCP251XFD_REG_INT_TEFIE … #define MCP251XFD_REG_INT_MODIE … #define MCP251XFD_REG_INT_TBCIE … #define MCP251XFD_REG_INT_RXIE … #define MCP251XFD_REG_INT_TXIE … #define MCP251XFD_REG_INT_IVMIF … #define MCP251XFD_REG_INT_WAKIF … #define MCP251XFD_REG_INT_CERRIF … #define MCP251XFD_REG_INT_SERRIF … #define MCP251XFD_REG_INT_RXOVIF … #define MCP251XFD_REG_INT_TXATIF … #define MCP251XFD_REG_INT_SPICRCIF … #define MCP251XFD_REG_INT_ECCIF … #define MCP251XFD_REG_INT_TEFIF … #define MCP251XFD_REG_INT_MODIF … #define MCP251XFD_REG_INT_TBCIF … #define MCP251XFD_REG_INT_RXIF … #define MCP251XFD_REG_INT_TXIF … /* These IRQ flags must be cleared by SW in the CAN_INT register */ #define MCP251XFD_REG_INT_IF_CLEARABLE_MASK … #define MCP251XFD_REG_RXIF … #define MCP251XFD_REG_TXIF … #define MCP251XFD_REG_RXOVIF … #define MCP251XFD_REG_TXATIF … #define MCP251XFD_REG_TXREQ … #define MCP251XFD_REG_TREC … #define MCP251XFD_REG_TREC_TXBO … #define MCP251XFD_REG_TREC_TXBP … #define MCP251XFD_REG_TREC_RXBP … #define MCP251XFD_REG_TREC_TXWARN … #define MCP251XFD_REG_TREC_RXWARN … #define MCP251XFD_REG_TREC_EWARN … #define MCP251XFD_REG_TREC_TEC_MASK … #define MCP251XFD_REG_TREC_REC_MASK … #define MCP251XFD_REG_BDIAG0 … #define MCP251XFD_REG_BDIAG0_DTERRCNT_MASK … #define MCP251XFD_REG_BDIAG0_DRERRCNT_MASK … #define MCP251XFD_REG_BDIAG0_NTERRCNT_MASK … #define MCP251XFD_REG_BDIAG0_NRERRCNT_MASK … #define MCP251XFD_REG_BDIAG1 … #define MCP251XFD_REG_BDIAG1_DLCMM … #define MCP251XFD_REG_BDIAG1_ESI … #define MCP251XFD_REG_BDIAG1_DCRCERR … #define MCP251XFD_REG_BDIAG1_DSTUFERR … #define MCP251XFD_REG_BDIAG1_DFORMERR … #define MCP251XFD_REG_BDIAG1_DBIT1ERR … #define MCP251XFD_REG_BDIAG1_DBIT0ERR … #define MCP251XFD_REG_BDIAG1_TXBOERR … #define MCP251XFD_REG_BDIAG1_NCRCERR … #define MCP251XFD_REG_BDIAG1_NSTUFERR … #define MCP251XFD_REG_BDIAG1_NFORMERR … #define MCP251XFD_REG_BDIAG1_NACKERR … #define MCP251XFD_REG_BDIAG1_NBIT1ERR … #define MCP251XFD_REG_BDIAG1_NBIT0ERR … #define MCP251XFD_REG_BDIAG1_BERR_MASK … #define MCP251XFD_REG_BDIAG1_EFMSGCNT_MASK … #define MCP251XFD_REG_TEFCON … #define MCP251XFD_REG_TEFCON_FSIZE_MASK … #define MCP251XFD_REG_TEFCON_FRESET … #define MCP251XFD_REG_TEFCON_UINC … #define MCP251XFD_REG_TEFCON_TEFTSEN … #define MCP251XFD_REG_TEFCON_TEFOVIE … #define MCP251XFD_REG_TEFCON_TEFFIE … #define MCP251XFD_REG_TEFCON_TEFHIE … #define MCP251XFD_REG_TEFCON_TEFNEIE … #define MCP251XFD_REG_TEFSTA … #define MCP251XFD_REG_TEFSTA_TEFOVIF … #define MCP251XFD_REG_TEFSTA_TEFFIF … #define MCP251XFD_REG_TEFSTA_TEFHIF … #define MCP251XFD_REG_TEFSTA_TEFNEIF … #define MCP251XFD_REG_TEFUA … #define MCP251XFD_REG_TXQCON … #define MCP251XFD_REG_TXQCON_PLSIZE_MASK … #define MCP251XFD_REG_TXQCON_PLSIZE_8 … #define MCP251XFD_REG_TXQCON_PLSIZE_12 … #define MCP251XFD_REG_TXQCON_PLSIZE_16 … #define MCP251XFD_REG_TXQCON_PLSIZE_20 … #define MCP251XFD_REG_TXQCON_PLSIZE_24 … #define MCP251XFD_REG_TXQCON_PLSIZE_32 … #define MCP251XFD_REG_TXQCON_PLSIZE_48 … #define MCP251XFD_REG_TXQCON_PLSIZE_64 … #define MCP251XFD_REG_TXQCON_FSIZE_MASK … #define MCP251XFD_REG_TXQCON_TXAT_UNLIMITED … #define MCP251XFD_REG_TXQCON_TXAT_THREE_SHOT … #define MCP251XFD_REG_TXQCON_TXAT_ONE_SHOT … #define MCP251XFD_REG_TXQCON_TXAT_MASK … #define MCP251XFD_REG_TXQCON_TXPRI_MASK … #define MCP251XFD_REG_TXQCON_FRESET … #define MCP251XFD_REG_TXQCON_TXREQ … #define MCP251XFD_REG_TXQCON_UINC … #define MCP251XFD_REG_TXQCON_TXEN … #define MCP251XFD_REG_TXQCON_TXATIE … #define MCP251XFD_REG_TXQCON_TXQEIE … #define MCP251XFD_REG_TXQCON_TXQNIE … #define MCP251XFD_REG_TXQSTA … #define MCP251XFD_REG_TXQSTA_TXQCI_MASK … #define MCP251XFD_REG_TXQSTA_TXABT … #define MCP251XFD_REG_TXQSTA_TXLARB … #define MCP251XFD_REG_TXQSTA_TXERR … #define MCP251XFD_REG_TXQSTA_TXATIF … #define MCP251XFD_REG_TXQSTA_TXQEIF … #define MCP251XFD_REG_TXQSTA_TXQNIF … #define MCP251XFD_REG_TXQUA … #define MCP251XFD_REG_FIFOCON(x) … #define MCP251XFD_REG_FIFOCON_PLSIZE_MASK … #define MCP251XFD_REG_FIFOCON_PLSIZE_8 … #define MCP251XFD_REG_FIFOCON_PLSIZE_12 … #define MCP251XFD_REG_FIFOCON_PLSIZE_16 … #define MCP251XFD_REG_FIFOCON_PLSIZE_20 … #define MCP251XFD_REG_FIFOCON_PLSIZE_24 … #define MCP251XFD_REG_FIFOCON_PLSIZE_32 … #define MCP251XFD_REG_FIFOCON_PLSIZE_48 … #define MCP251XFD_REG_FIFOCON_PLSIZE_64 … #define MCP251XFD_REG_FIFOCON_FSIZE_MASK … #define MCP251XFD_REG_FIFOCON_TXAT_MASK … #define MCP251XFD_REG_FIFOCON_TXAT_ONE_SHOT … #define MCP251XFD_REG_FIFOCON_TXAT_THREE_SHOT … #define MCP251XFD_REG_FIFOCON_TXAT_UNLIMITED … #define MCP251XFD_REG_FIFOCON_TXPRI_MASK … #define MCP251XFD_REG_FIFOCON_FRESET … #define MCP251XFD_REG_FIFOCON_TXREQ … #define MCP251XFD_REG_FIFOCON_UINC … #define MCP251XFD_REG_FIFOCON_TXEN … #define MCP251XFD_REG_FIFOCON_RTREN … #define MCP251XFD_REG_FIFOCON_RXTSEN … #define MCP251XFD_REG_FIFOCON_TXATIE … #define MCP251XFD_REG_FIFOCON_RXOVIE … #define MCP251XFD_REG_FIFOCON_TFERFFIE … #define MCP251XFD_REG_FIFOCON_TFHRFHIE … #define MCP251XFD_REG_FIFOCON_TFNRFNIE … #define MCP251XFD_REG_FIFOSTA(x) … #define MCP251XFD_REG_FIFOSTA_FIFOCI_MASK … #define MCP251XFD_REG_FIFOSTA_TXABT … #define MCP251XFD_REG_FIFOSTA_TXLARB … #define MCP251XFD_REG_FIFOSTA_TXERR … #define MCP251XFD_REG_FIFOSTA_TXATIF … #define MCP251XFD_REG_FIFOSTA_RXOVIF … #define MCP251XFD_REG_FIFOSTA_TFERFFIF … #define MCP251XFD_REG_FIFOSTA_TFHRFHIF … #define MCP251XFD_REG_FIFOSTA_TFNRFNIF … #define MCP251XFD_REG_FIFOUA(x) … #define MCP251XFD_REG_FLTCON(x) … #define MCP251XFD_REG_FLTCON_FLTEN3 … #define MCP251XFD_REG_FLTCON_F3BP_MASK … #define MCP251XFD_REG_FLTCON_FLTEN2 … #define MCP251XFD_REG_FLTCON_F2BP_MASK … #define MCP251XFD_REG_FLTCON_FLTEN1 … #define MCP251XFD_REG_FLTCON_F1BP_MASK … #define MCP251XFD_REG_FLTCON_FLTEN0 … #define MCP251XFD_REG_FLTCON_F0BP_MASK … #define MCP251XFD_REG_FLTCON_FLTEN(x) … #define MCP251XFD_REG_FLTCON_FLT_MASK(x) … #define MCP251XFD_REG_FLTCON_FBP(x, fifo) … #define MCP251XFD_REG_FLTOBJ(x) … #define MCP251XFD_REG_FLTOBJ_EXIDE … #define MCP251XFD_REG_FLTOBJ_SID11 … #define MCP251XFD_REG_FLTOBJ_EID_MASK … #define MCP251XFD_REG_FLTOBJ_SID_MASK … #define MCP251XFD_REG_FLTMASK(x) … #define MCP251XFD_REG_MASK_MIDE … #define MCP251XFD_REG_MASK_MSID11 … #define MCP251XFD_REG_MASK_MEID_MASK … #define MCP251XFD_REG_MASK_MSID_MASK … /* RAM */ #define MCP251XFD_RAM_START … #define MCP251XFD_RAM_SIZE … /* Message Object */ #define MCP251XFD_OBJ_ID_SID11 … #define MCP251XFD_OBJ_ID_EID_MASK … #define MCP251XFD_OBJ_ID_SID_MASK … #define MCP251XFD_OBJ_FLAGS_SEQ_MCP2518FD_MASK … #define MCP251XFD_OBJ_FLAGS_SEQ_MCP2517FD_MASK … #define MCP251XFD_OBJ_FLAGS_SEQ_MASK … #define MCP251XFD_OBJ_FLAGS_ESI … #define MCP251XFD_OBJ_FLAGS_FDF … #define MCP251XFD_OBJ_FLAGS_BRS … #define MCP251XFD_OBJ_FLAGS_RTR … #define MCP251XFD_OBJ_FLAGS_IDE … #define MCP251XFD_OBJ_FLAGS_DLC_MASK … #define MCP251XFD_REG_FRAME_EFF_SID_MASK … #define MCP251XFD_REG_FRAME_EFF_EID_MASK … /* MCP2517/18FD SFR */ #define MCP251XFD_REG_OSC … #define MCP251XFD_REG_OSC_SCLKRDY … #define MCP251XFD_REG_OSC_OSCRDY … #define MCP251XFD_REG_OSC_PLLRDY … #define MCP251XFD_REG_OSC_CLKODIV_10 … #define MCP251XFD_REG_OSC_CLKODIV_4 … #define MCP251XFD_REG_OSC_CLKODIV_2 … #define MCP251XFD_REG_OSC_CLKODIV_1 … #define MCP251XFD_REG_OSC_CLKODIV_MASK … #define MCP251XFD_REG_OSC_SCLKDIV … #define MCP251XFD_REG_OSC_LPMEN … #define MCP251XFD_REG_OSC_OSCDIS … #define MCP251XFD_REG_OSC_PLLEN … #define MCP251XFD_REG_IOCON … #define MCP251XFD_REG_IOCON_INTOD … #define MCP251XFD_REG_IOCON_SOF … #define MCP251XFD_REG_IOCON_TXCANOD … #define MCP251XFD_REG_IOCON_PM1 … #define MCP251XFD_REG_IOCON_PM0 … #define MCP251XFD_REG_IOCON_GPIO1 … #define MCP251XFD_REG_IOCON_GPIO0 … #define MCP251XFD_REG_IOCON_LAT1 … #define MCP251XFD_REG_IOCON_LAT0 … #define MCP251XFD_REG_IOCON_XSTBYEN … #define MCP251XFD_REG_IOCON_TRIS1 … #define MCP251XFD_REG_IOCON_TRIS0 … #define MCP251XFD_REG_CRC … #define MCP251XFD_REG_CRC_FERRIE … #define MCP251XFD_REG_CRC_CRCERRIE … #define MCP251XFD_REG_CRC_FERRIF … #define MCP251XFD_REG_CRC_CRCERRIF … #define MCP251XFD_REG_CRC_IF_MASK … #define MCP251XFD_REG_CRC_MASK … #define MCP251XFD_REG_ECCCON … #define MCP251XFD_REG_ECCCON_PARITY_MASK … #define MCP251XFD_REG_ECCCON_DEDIE … #define MCP251XFD_REG_ECCCON_SECIE … #define MCP251XFD_REG_ECCCON_ECCEN … #define MCP251XFD_REG_ECCSTAT … #define MCP251XFD_REG_ECCSTAT_ERRADDR_MASK … #define MCP251XFD_REG_ECCSTAT_IF_MASK … #define MCP251XFD_REG_ECCSTAT_DEDIF … #define MCP251XFD_REG_ECCSTAT_SECIF … #define MCP251XFD_REG_DEVID … #define MCP251XFD_REG_DEVID_ID_MASK … #define MCP251XFD_REG_DEVID_REV_MASK … /* SPI commands */ #define MCP251XFD_SPI_INSTRUCTION_RESET … #define MCP251XFD_SPI_INSTRUCTION_WRITE … #define MCP251XFD_SPI_INSTRUCTION_READ … #define MCP251XFD_SPI_INSTRUCTION_WRITE_CRC … #define MCP251XFD_SPI_INSTRUCTION_READ_CRC … #define MCP251XFD_SPI_INSTRUCTION_WRITE_CRC_SAFE … #define MCP251XFD_SPI_ADDRESS_MASK … #define MCP251XFD_SYSCLOCK_HZ_MAX … #define MCP251XFD_SYSCLOCK_HZ_MIN … #define MCP251XFD_SPICLOCK_HZ_MAX … #define MCP251XFD_TIMESTAMP_WORK_DELAY_SEC … static_assert(…); #define MCP251XFD_OSC_PLL_MULTIPLIER … #define MCP251XFD_OSC_STAB_SLEEP_US … #define MCP251XFD_OSC_STAB_TIMEOUT_US … #define MCP251XFD_POLL_SLEEP_US … #define MCP251XFD_POLL_TIMEOUT_US … #define MCP251XFD_FRAME_LEN_MAX_BITS … /* Misc */ #define MCP251XFD_NAPI_WEIGHT … #define MCP251XFD_SOFTRESET_RETRIES_MAX … #define MCP251XFD_READ_CRC_RETRIES_MAX … #define MCP251XFD_ECC_CNT_MAX … #define MCP251XFD_SANITIZE_SPI … #define MCP251XFD_SANITIZE_CAN … /* FIFO and Ring */ #define MCP251XFD_FIFO_TEF_NUM … #define MCP251XFD_FIFO_RX_NUM … #define MCP251XFD_FIFO_TX_NUM … #define MCP251XFD_FIFO_DEPTH … #define MCP251XFD_RX_OBJ_NUM_MIN … #define MCP251XFD_RX_OBJ_NUM_MAX … #define MCP251XFD_RX_FIFO_DEPTH_MIN … #define MCP251XFD_RX_FIFO_DEPTH_COALESCE_MIN … #define MCP251XFD_TX_OBJ_NUM_MIN … #define MCP251XFD_TX_OBJ_NUM_MAX … #define MCP251XFD_TX_OBJ_NUM_CAN_DEFAULT … #define MCP251XFD_TX_OBJ_NUM_CANFD_DEFAULT … #define MCP251XFD_TX_FIFO_DEPTH_MIN … #define MCP251XFD_TX_FIFO_DEPTH_COALESCE_MIN … static_assert(…); static_assert(…); static_assert(…); /* Silence TX MAB overflow warnings */ #define MCP251XFD_QUIRK_MAB_NO_WARN … /* Use CRC to access registers */ #define MCP251XFD_QUIRK_CRC_REG … /* Use CRC to access RX/TEF-RAM */ #define MCP251XFD_QUIRK_CRC_RX … /* Use CRC to access TX-RAM */ #define MCP251XFD_QUIRK_CRC_TX … /* Enable ECC for RAM */ #define MCP251XFD_QUIRK_ECC … /* Use Half Duplex SPI transfers */ #define MCP251XFD_QUIRK_HALF_DUPLEX … struct mcp251xfd_hw_tef_obj { … }; /* The tx_obj_raw version is used in spi async, i.e. without * regmap. We have to take care of endianness ourselves. */ struct __packed mcp251xfd_hw_tx_obj_raw { … }; struct mcp251xfd_hw_tx_obj_can { … }; struct mcp251xfd_hw_tx_obj_canfd { … }; struct mcp251xfd_hw_rx_obj_can { … }; struct mcp251xfd_hw_rx_obj_canfd { … }; struct __packed mcp251xfd_buf_cmd { … }; struct __packed mcp251xfd_buf_cmd_crc { … }; mcp251xfd_tx_obj_load_buf ____cacheline_aligned; mcp251xfd_write_reg_buf ____cacheline_aligned; struct mcp251xfd_tx_obj { … }; struct mcp251xfd_tef_ring { … }; struct mcp251xfd_tx_ring { … }; struct mcp251xfd_rx_ring { … }; struct __packed mcp251xfd_map_buf_nocrc { … } ____cacheline_aligned; struct __packed mcp251xfd_map_buf_crc { … } ____cacheline_aligned; struct mcp251xfd_ecc { … }; struct mcp251xfd_regs_status { … }; enum mcp251xfd_model { … }; struct mcp251xfd_devtype_data { … }; enum mcp251xfd_flags { … }; struct mcp251xfd_priv { … }; #define MCP251XFD_IS(_model) … MCP251XFD_IS(2517FD); MCP251XFD_IS(2518FD); MCP251XFD_IS(251863); MCP251XFD_IS(251XFD); static inline bool mcp251xfd_is_fd_mode(const struct mcp251xfd_priv *priv) { … } static inline u8 mcp251xfd_first_byte_set(u32 mask) { … } static inline u8 mcp251xfd_last_byte_set(u32 mask) { … } static inline __be16 mcp251xfd_cmd_reset(void) { … } static inline void mcp251xfd_spi_cmd_read_nocrc(struct mcp251xfd_buf_cmd *cmd, u16 addr) { … } static inline void mcp251xfd_spi_cmd_write_nocrc(struct mcp251xfd_buf_cmd *cmd, u16 addr) { … } static inline bool mcp251xfd_reg_in_ram(unsigned int reg) { … } static inline void __mcp251xfd_spi_cmd_crc_set_len(struct mcp251xfd_buf_cmd_crc *cmd, u16 len, bool in_ram) { … } static inline void mcp251xfd_spi_cmd_crc_set_len_in_ram(struct mcp251xfd_buf_cmd_crc *cmd, u16 len) { … } static inline void mcp251xfd_spi_cmd_crc_set_len_in_reg(struct mcp251xfd_buf_cmd_crc *cmd, u16 len) { … } static inline void mcp251xfd_spi_cmd_read_crc_set_addr(struct mcp251xfd_buf_cmd_crc *cmd, u16 addr) { … } static inline void mcp251xfd_spi_cmd_read_crc(struct mcp251xfd_buf_cmd_crc *cmd, u16 addr, u16 len) { … } static inline void mcp251xfd_spi_cmd_write_crc_set_addr(struct mcp251xfd_buf_cmd_crc *cmd, u16 addr) { … } static inline void mcp251xfd_spi_cmd_write_safe_set_addr(struct mcp251xfd_buf_cmd *cmd, u16 addr) { … } static inline void mcp251xfd_spi_cmd_write_crc(struct mcp251xfd_buf_cmd_crc *cmd, u16 addr, u16 len) { … } static inline u8 * mcp251xfd_spi_cmd_write(const struct mcp251xfd_priv *priv, union mcp251xfd_write_reg_buf *write_reg_buf, u16 addr, u8 len) { … } static inline int mcp251xfd_get_timestamp_raw(const struct mcp251xfd_priv *priv, u32 *ts_raw) { … } static inline void mcp251xfd_skb_set_timestamp(struct sk_buff *skb, u64 ns) { … } static inline void mcp251xfd_skb_set_timestamp_raw(const struct mcp251xfd_priv *priv, struct sk_buff *skb, u32 ts_raw) { … } static inline u16 mcp251xfd_get_tef_obj_addr(u8 n) { … } static inline u16 mcp251xfd_get_tx_obj_addr(const struct mcp251xfd_tx_ring *ring, u8 n) { … } static inline u16 mcp251xfd_get_rx_obj_addr(const struct mcp251xfd_rx_ring *ring, u8 n) { … } static inline int mcp251xfd_tx_tail_get_from_chip(const struct mcp251xfd_priv *priv, u8 *tx_tail) { … } static inline u8 mcp251xfd_get_tef_head(const struct mcp251xfd_priv *priv) { … } static inline u8 mcp251xfd_get_tef_tail(const struct mcp251xfd_priv *priv) { … } static inline u8 mcp251xfd_get_tef_linear_len(const struct mcp251xfd_priv *priv, u8 len) { … } static inline u8 mcp251xfd_get_tx_head(const struct mcp251xfd_tx_ring *ring) { … } static inline u8 mcp251xfd_get_tx_tail(const struct mcp251xfd_tx_ring *ring) { … } static inline u8 mcp251xfd_get_tx_free(const struct mcp251xfd_tx_ring *ring) { … } static inline int mcp251xfd_get_tx_nr_by_addr(const struct mcp251xfd_tx_ring *tx_ring, u8 *nr, u16 addr) { … } static inline u8 mcp251xfd_get_rx_head(const struct mcp251xfd_rx_ring *ring) { … } static inline u8 mcp251xfd_get_rx_tail(const struct mcp251xfd_rx_ring *ring) { … } static inline u8 mcp251xfd_get_rx_linear_len(const struct mcp251xfd_rx_ring *ring, u8 len) { … } #define mcp251xfd_for_each_tx_obj(ring, _obj, n) … #define mcp251xfd_for_each_rx_ring(priv, ring, n) … int mcp251xfd_chip_fifo_init(const struct mcp251xfd_priv *priv); u16 mcp251xfd_crc16_compute2(const void *cmd, size_t cmd_size, const void *data, size_t data_size); u16 mcp251xfd_crc16_compute(const void *data, size_t data_size); void mcp251xfd_ethtool_init(struct mcp251xfd_priv *priv); int mcp251xfd_regmap_init(struct mcp251xfd_priv *priv); extern const struct can_ram_config mcp251xfd_ram_config; int mcp251xfd_ring_init(struct mcp251xfd_priv *priv); void mcp251xfd_ring_free(struct mcp251xfd_priv *priv); int mcp251xfd_ring_alloc(struct mcp251xfd_priv *priv); int mcp251xfd_handle_rxif(struct mcp251xfd_priv *priv); int mcp251xfd_handle_tefif(struct mcp251xfd_priv *priv); void mcp251xfd_timestamp_init(struct mcp251xfd_priv *priv); void mcp251xfd_timestamp_start(struct mcp251xfd_priv *priv); void mcp251xfd_timestamp_stop(struct mcp251xfd_priv *priv); void mcp251xfd_tx_obj_write_sync(struct work_struct *work); netdev_tx_t mcp251xfd_start_xmit(struct sk_buff *skb, struct net_device *ndev); #if IS_ENABLED(CONFIG_DEV_COREDUMP) void mcp251xfd_dump(const struct mcp251xfd_priv *priv); #else static inline void mcp251xfd_dump(const struct mcp251xfd_priv *priv) { } #endif #endif
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