/* SPDX-License-Identifier: GPL-2.0-or-later */ /******************************************************************************* * * CTU CAN FD IP Core * * Copyright (C) 2015-2018 Ondrej Ille <[email protected]> FEE CTU * Copyright (C) 2018-2022 Ondrej Ille <[email protected]> self-funded * Copyright (C) 2018-2019 Martin Jerabek <[email protected]> FEE CTU * Copyright (C) 2018-2022 Pavel Pisa <[email protected]> FEE CTU/self-funded * * Project advisors: * Jiri Novak <[email protected]> * Pavel Pisa <[email protected]> * * Department of Measurement (http://meas.fel.cvut.cz/) * Faculty of Electrical Engineering (http://www.fel.cvut.cz) * Czech Technical University (http://www.cvut.cz/) ******************************************************************************/ /* This file is autogenerated, DO NOT EDIT! */ #ifndef __CTU_CAN_FD_CAN_FD_REGISTER_MAP__ #define __CTU_CAN_FD_CAN_FD_REGISTER_MAP__ #include <linux/bits.h> /* CAN_Registers memory map */ enum ctu_can_fd_can_registers { … }; /* Control_registers memory region */ /* DEVICE_ID VERSION registers */ #define REG_DEVICE_ID_DEVICE_ID … #define REG_DEVICE_ID_VER_MINOR … #define REG_DEVICE_ID_VER_MAJOR … /* MODE SETTINGS registers */ #define REG_MODE_RST … #define REG_MODE_BMM … #define REG_MODE_STM … #define REG_MODE_AFM … #define REG_MODE_FDE … #define REG_MODE_TTTM … #define REG_MODE_ROM … #define REG_MODE_ACF … #define REG_MODE_TSTM … #define REG_MODE_RXBAM … #define REG_MODE_SAM … #define REG_MODE_RTRLE … #define REG_MODE_RTRTH … #define REG_MODE_ILBP … #define REG_MODE_ENA … #define REG_MODE_NISOFD … #define REG_MODE_PEX … #define REG_MODE_TBFBO … #define REG_MODE_FDRF … /* STATUS registers */ #define REG_STATUS_RXNE … #define REG_STATUS_DOR … #define REG_STATUS_TXNF … #define REG_STATUS_EFT … #define REG_STATUS_RXS … #define REG_STATUS_TXS … #define REG_STATUS_EWL … #define REG_STATUS_IDLE … #define REG_STATUS_PEXS … #define REG_STATUS_STCNT … /* COMMAND registers */ #define REG_COMMAND_RXRPMV … #define REG_COMMAND_RRB … #define REG_COMMAND_CDO … #define REG_COMMAND_ERCRST … #define REG_COMMAND_RXFCRST … #define REG_COMMAND_TXFCRST … #define REG_COMMAND_CPEXS … /* INT_STAT registers */ #define REG_INT_STAT_RXI … #define REG_INT_STAT_TXI … #define REG_INT_STAT_EWLI … #define REG_INT_STAT_DOI … #define REG_INT_STAT_FCSI … #define REG_INT_STAT_ALI … #define REG_INT_STAT_BEI … #define REG_INT_STAT_OFI … #define REG_INT_STAT_RXFI … #define REG_INT_STAT_BSI … #define REG_INT_STAT_RBNEI … #define REG_INT_STAT_TXBHCI … /* INT_ENA_SET registers */ #define REG_INT_ENA_SET_INT_ENA_SET … /* INT_ENA_CLR registers */ #define REG_INT_ENA_CLR_INT_ENA_CLR … /* INT_MASK_SET registers */ #define REG_INT_MASK_SET_INT_MASK_SET … /* INT_MASK_CLR registers */ #define REG_INT_MASK_CLR_INT_MASK_CLR … /* BTR registers */ #define REG_BTR_PROP … #define REG_BTR_PH1 … #define REG_BTR_PH2 … #define REG_BTR_BRP … #define REG_BTR_SJW … /* BTR_FD registers */ #define REG_BTR_FD_PROP_FD … #define REG_BTR_FD_PH1_FD … #define REG_BTR_FD_PH2_FD … #define REG_BTR_FD_BRP_FD … #define REG_BTR_FD_SJW_FD … /* EWL ERP FAULT_STATE registers */ #define REG_EWL_EW_LIMIT … #define REG_EWL_ERP_LIMIT … #define REG_EWL_ERA … #define REG_EWL_ERP … #define REG_EWL_BOF … /* REC TEC registers */ #define REG_REC_REC_VAL … #define REG_REC_TEC_VAL … /* ERR_NORM ERR_FD registers */ #define REG_ERR_NORM_ERR_NORM_VAL … #define REG_ERR_NORM_ERR_FD_VAL … /* CTR_PRES registers */ #define REG_CTR_PRES_CTPV … #define REG_CTR_PRES_PTX … #define REG_CTR_PRES_PRX … #define REG_CTR_PRES_ENORM … #define REG_CTR_PRES_EFD … /* FILTER_A_MASK registers */ #define REG_FILTER_A_MASK_BIT_MASK_A_VAL … /* FILTER_A_VAL registers */ #define REG_FILTER_A_VAL_BIT_VAL_A_VAL … /* FILTER_B_MASK registers */ #define REG_FILTER_B_MASK_BIT_MASK_B_VAL … /* FILTER_B_VAL registers */ #define REG_FILTER_B_VAL_BIT_VAL_B_VAL … /* FILTER_C_MASK registers */ #define REG_FILTER_C_MASK_BIT_MASK_C_VAL … /* FILTER_C_VAL registers */ #define REG_FILTER_C_VAL_BIT_VAL_C_VAL … /* FILTER_RAN_LOW registers */ #define REG_FILTER_RAN_LOW_BIT_RAN_LOW_VAL … /* FILTER_RAN_HIGH registers */ #define REG_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL … /* FILTER_CONTROL FILTER_STATUS registers */ #define REG_FILTER_CONTROL_FANB … #define REG_FILTER_CONTROL_FANE … #define REG_FILTER_CONTROL_FAFB … #define REG_FILTER_CONTROL_FAFE … #define REG_FILTER_CONTROL_FBNB … #define REG_FILTER_CONTROL_FBNE … #define REG_FILTER_CONTROL_FBFB … #define REG_FILTER_CONTROL_FBFE … #define REG_FILTER_CONTROL_FCNB … #define REG_FILTER_CONTROL_FCNE … #define REG_FILTER_CONTROL_FCFB … #define REG_FILTER_CONTROL_FCFE … #define REG_FILTER_CONTROL_FRNB … #define REG_FILTER_CONTROL_FRNE … #define REG_FILTER_CONTROL_FRFB … #define REG_FILTER_CONTROL_FRFE … #define REG_FILTER_CONTROL_SFA … #define REG_FILTER_CONTROL_SFB … #define REG_FILTER_CONTROL_SFC … #define REG_FILTER_CONTROL_SFR … /* RX_MEM_INFO registers */ #define REG_RX_MEM_INFO_RX_BUFF_SIZE … #define REG_RX_MEM_INFO_RX_MEM_FREE … /* RX_POINTERS registers */ #define REG_RX_POINTERS_RX_WPP … #define REG_RX_POINTERS_RX_RPP … /* RX_STATUS RX_SETTINGS registers */ #define REG_RX_STATUS_RXE … #define REG_RX_STATUS_RXF … #define REG_RX_STATUS_RXMOF … #define REG_RX_STATUS_RXFRC … #define REG_RX_STATUS_RTSOP … /* RX_DATA registers */ #define REG_RX_DATA_RX_DATA … /* TX_STATUS registers */ #define REG_TX_STATUS_TX1S … #define REG_TX_STATUS_TX2S … #define REG_TX_STATUS_TX3S … #define REG_TX_STATUS_TX4S … #define REG_TX_STATUS_TX5S … #define REG_TX_STATUS_TX6S … #define REG_TX_STATUS_TX7S … #define REG_TX_STATUS_TX8S … /* TX_COMMAND TXTB_INFO registers */ #define REG_TX_COMMAND_TXCE … #define REG_TX_COMMAND_TXCR … #define REG_TX_COMMAND_TXCA … #define REG_TX_COMMAND_TXB1 … #define REG_TX_COMMAND_TXB2 … #define REG_TX_COMMAND_TXB3 … #define REG_TX_COMMAND_TXB4 … #define REG_TX_COMMAND_TXB5 … #define REG_TX_COMMAND_TXB6 … #define REG_TX_COMMAND_TXB7 … #define REG_TX_COMMAND_TXB8 … #define REG_TX_COMMAND_TXT_BUFFER_COUNT … /* TX_PRIORITY registers */ #define REG_TX_PRIORITY_TXT1P … #define REG_TX_PRIORITY_TXT2P … #define REG_TX_PRIORITY_TXT3P … #define REG_TX_PRIORITY_TXT4P … #define REG_TX_PRIORITY_TXT5P … #define REG_TX_PRIORITY_TXT6P … #define REG_TX_PRIORITY_TXT7P … #define REG_TX_PRIORITY_TXT8P … /* ERR_CAPT RETR_CTR ALC TS_INFO registers */ #define REG_ERR_CAPT_ERR_POS … #define REG_ERR_CAPT_ERR_TYPE … #define REG_ERR_CAPT_RETR_CTR_VAL … #define REG_ERR_CAPT_ALC_BIT … #define REG_ERR_CAPT_ALC_ID_FIELD … #define REG_ERR_CAPT_TS_BITS … /* TRV_DELAY SSP_CFG registers */ #define REG_TRV_DELAY_TRV_DELAY_VALUE … #define REG_TRV_DELAY_SSP_OFFSET … #define REG_TRV_DELAY_SSP_SRC … /* RX_FR_CTR registers */ #define REG_RX_FR_CTR_RX_FR_CTR_VAL … /* TX_FR_CTR registers */ #define REG_TX_FR_CTR_TX_FR_CTR_VAL … /* DEBUG_REGISTER registers */ #define REG_DEBUG_REGISTER_STUFF_COUNT … #define REG_DEBUG_REGISTER_DESTUFF_COUNT … #define REG_DEBUG_REGISTER_PC_ARB … #define REG_DEBUG_REGISTER_PC_CON … #define REG_DEBUG_REGISTER_PC_DAT … #define REG_DEBUG_REGISTER_PC_STC … #define REG_DEBUG_REGISTER_PC_CRC … #define REG_DEBUG_REGISTER_PC_CRCD … #define REG_DEBUG_REGISTER_PC_ACK … #define REG_DEBUG_REGISTER_PC_ACKD … #define REG_DEBUG_REGISTER_PC_EOF … #define REG_DEBUG_REGISTER_PC_INT … #define REG_DEBUG_REGISTER_PC_SUSP … #define REG_DEBUG_REGISTER_PC_OVR … #define REG_DEBUG_REGISTER_PC_SOF … /* YOLO_REG registers */ #define REG_YOLO_REG_YOLO_VAL … /* TIMESTAMP_LOW registers */ #define REG_TIMESTAMP_LOW_TIMESTAMP_LOW … /* TIMESTAMP_HIGH registers */ #define REG_TIMESTAMP_HIGH_TIMESTAMP_HIGH … #endif
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