// SPDX-License-Identifier: GPL-2.0-only /* Copyright (C) 2007, 2011 Wolfgang Grandegger <[email protected]> * Copyright (C) 2012 Stephane Grosjean <[email protected]> * * Derived from the PCAN project file driver/src/pcan_pci.c: * * Copyright (C) 2001-2006 PEAK System-Technik GmbH */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/interrupt.h> #include <linux/netdevice.h> #include <linux/delay.h> #include <linux/pci.h> #include <linux/io.h> #include <linux/can.h> #include <linux/can/dev.h> #include "peak_canfd_user.h" MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; #define PCIEFD_DRV_NAME … #define PEAK_PCI_VENDOR_ID … #define PEAK_PCIEFD_ID … #define PCAN_CPCIEFD_ID … #define PCAN_PCIE104FD_ID … #define PCAN_MINIPCIEFD_ID … #define PCAN_PCIEFD_OEM_ID … #define PCAN_M2_ID … /* PEAK PCIe board access description */ #define PCIEFD_BAR0_SIZE … #define PCIEFD_RX_DMA_SIZE … #define PCIEFD_TX_DMA_SIZE … #define PCIEFD_TX_PAGE_SIZE … /* System Control Registers */ #define PCIEFD_REG_SYS_CTL_SET … #define PCIEFD_REG_SYS_CTL_CLR … /* Version info registers */ #define PCIEFD_REG_SYS_VER1 … #define PCIEFD_REG_SYS_VER2 … #define PCIEFD_FW_VERSION(x, y, z) … /* System Control Registers Bits */ #define PCIEFD_SYS_CTL_TS_RST … #define PCIEFD_SYS_CTL_CLK_EN … /* CAN-FD channel addresses */ #define PCIEFD_CANX_OFF(c) … #define PCIEFD_ECHO_SKB_MAX … /* CAN-FD channel registers */ #define PCIEFD_REG_CAN_MISC … #define PCIEFD_REG_CAN_CLK_SEL … #define PCIEFD_REG_CAN_CMD_PORT_L … #define PCIEFD_REG_CAN_CMD_PORT_H … #define PCIEFD_REG_CAN_TX_REQ_ACC … #define PCIEFD_REG_CAN_TX_CTL_SET … #define PCIEFD_REG_CAN_TX_CTL_CLR … #define PCIEFD_REG_CAN_TX_DMA_ADDR_L … #define PCIEFD_REG_CAN_TX_DMA_ADDR_H … #define PCIEFD_REG_CAN_RX_CTL_SET … #define PCIEFD_REG_CAN_RX_CTL_CLR … #define PCIEFD_REG_CAN_RX_CTL_WRT … #define PCIEFD_REG_CAN_RX_CTL_ACK … #define PCIEFD_REG_CAN_RX_DMA_ADDR_L … #define PCIEFD_REG_CAN_RX_DMA_ADDR_H … /* CAN-FD channel misc register bits */ #define CANFD_MISC_TS_RST … /* CAN-FD channel Clock SELector Source & DIVider */ #define CANFD_CLK_SEL_DIV_MASK … #define CANFD_CLK_SEL_DIV_60MHZ … #define CANFD_CLK_SEL_DIV_40MHZ … #define CANFD_CLK_SEL_DIV_30MHZ … #define CANFD_CLK_SEL_DIV_24MHZ … #define CANFD_CLK_SEL_DIV_20MHZ … #define CANFD_CLK_SEL_SRC_MASK … #define CANFD_CLK_SEL_SRC_240MHZ … #define CANFD_CLK_SEL_SRC_80MHZ … #define CANFD_CLK_SEL_20MHZ … #define CANFD_CLK_SEL_24MHZ … #define CANFD_CLK_SEL_30MHZ … #define CANFD_CLK_SEL_40MHZ … #define CANFD_CLK_SEL_60MHZ … #define CANFD_CLK_SEL_80MHZ … /* CAN-FD channel Rx/Tx control register bits */ #define CANFD_CTL_UNC_BIT … #define CANFD_CTL_RST_BIT … #define CANFD_CTL_IEN_BIT … /* Rx IRQ Count and Time Limits */ #define CANFD_CTL_IRQ_CL_DEF … #define CANFD_CTL_IRQ_TL_DEF … /* Tx anticipation window (link logical address should be aligned on 2K * boundary) */ #define PCIEFD_TX_PAGE_COUNT … #define CANFD_MSG_LNK_TX … /* 32-bits IRQ status fields, heading Rx DMA area */ static inline int pciefd_irq_tag(u32 irq_status) { … } static inline int pciefd_irq_rx_cnt(u32 irq_status) { … } static inline int pciefd_irq_is_lnk(u32 irq_status) { … } /* Rx record */ struct pciefd_rx_dma { … } __packed __aligned(…); /* Tx Link record */ struct pciefd_tx_link { … } __packed __aligned(…); /* Tx page descriptor */ struct pciefd_page { … }; /* CAN-FD channel object */ struct pciefd_board; struct pciefd_can { … }; /* PEAK-PCIe FD board object */ struct pciefd_board { … }; /* supported device ids. */ static const struct pci_device_id peak_pciefd_tbl[] = …; MODULE_DEVICE_TABLE(pci, peak_pciefd_tbl); /* read a 32 bits value from a SYS block register */ static inline u32 pciefd_sys_readreg(const struct pciefd_board *priv, u16 reg) { … } /* write a 32 bits value into a SYS block register */ static inline void pciefd_sys_writereg(const struct pciefd_board *priv, u32 val, u16 reg) { … } /* read a 32 bits value from CAN-FD block register */ static inline u32 pciefd_can_readreg(const struct pciefd_can *priv, u16 reg) { … } /* write a 32 bits value into a CAN-FD block register */ static inline void pciefd_can_writereg(const struct pciefd_can *priv, u32 val, u16 reg) { … } /* give a channel logical Rx DMA address to the board */ static void pciefd_can_setup_rx_dma(struct pciefd_can *priv) { … } /* clear channel logical Rx DMA address from the board */ static void pciefd_can_clear_rx_dma(struct pciefd_can *priv) { … } /* give a channel logical Tx DMA address to the board */ static void pciefd_can_setup_tx_dma(struct pciefd_can *priv) { … } /* clear channel logical Tx DMA address from the board */ static void pciefd_can_clear_tx_dma(struct pciefd_can *priv) { … } static void pciefd_can_ack_rx_dma(struct pciefd_can *priv) { … } /* IRQ handler */ static irqreturn_t pciefd_irq_handler(int irq, void *arg) { … } static int pciefd_enable_tx_path(struct peak_canfd_priv *ucan) { … } /* board specific CANFD command pre-processing */ static int pciefd_pre_cmd(struct peak_canfd_priv *ucan) { … } /* write a command */ static int pciefd_write_cmd(struct peak_canfd_priv *ucan) { … } /* board specific CANFD command post-processing */ static int pciefd_post_cmd(struct peak_canfd_priv *ucan) { … } static void *pciefd_alloc_tx_msg(struct peak_canfd_priv *ucan, u16 msg_size, int *room_left) { … } static int pciefd_write_tx_msg(struct peak_canfd_priv *ucan, struct pucan_tx_msg *msg) { … } /* probe for CAN-FD channel #pciefd_board->can_count */ static int pciefd_can_probe(struct pciefd_board *pciefd) { … } /* remove a CAN-FD channel by releasing all of its resources */ static void pciefd_can_remove(struct pciefd_can *priv) { … } /* remove all CAN-FD channels by releasing their own resources */ static void pciefd_can_remove_all(struct pciefd_board *pciefd) { … } /* probe for the entire device */ static int peak_pciefd_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { … } /* free the board structure object, as well as its resources: */ static void peak_pciefd_remove(struct pci_dev *pdev) { … } static struct pci_driver peak_pciefd_driver = …; module_pci_driver(…) …;
Codebase Browser
linux