// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008-2010 Pavel Cheblakov <[email protected]> * * Derived from the ems_pci.c driver: * Copyright (C) 2007 Wolfgang Grandegger <[email protected]> * Copyright (C) 2008 Markus Plessing <[email protected]> * Copyright (C) 2008 Sebastian Haas <[email protected]> */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/interrupt.h> #include <linux/netdevice.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/pci.h> #include <linux/can/dev.h> #include <linux/io.h> #include "sja1000.h" #define DRV_NAME … MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; #define PLX_PCI_MAX_CHAN … struct plx_pci_card { … }; #define PLX_PCI_CAN_CLOCK … /* PLX9030/9050/9052 registers */ #define PLX_INTCSR … #define PLX_CNTRL … #define PLX_LINT1_EN … #define PLX_LINT1_POL … #define PLX_LINT2_EN … #define PLX_LINT2_POL … #define PLX_PCI_INT_EN … #define PLX_PCI_RESET … /* PLX9056 registers */ #define PLX9056_INTCSR … #define PLX9056_CNTRL … #define PLX9056_LINTI … #define PLX9056_PCI_INT_EN … #define PLX9056_PCI_RCR … /* * The board configuration is probably following: * RX1 is connected to ground. * TX1 is not connected. * CLKO is not connected. * Setting the OCR register to 0xDA is a good idea. * This means normal output mode, push-pull and the correct polarity. */ #define PLX_PCI_OCR … /* OCR setting for ASEM Dual CAN raw */ #define ASEM_PCI_OCR … /* * In the CDR register, you should set CBP to 1. * You will probably also want to set the clock divider value to 7 * (meaning direct oscillator output) because the second SJA1000 chip * is driven by the first one CLKOUT output. */ #define PLX_PCI_CDR … /* SJA1000 Control Register in the BasicCAN Mode */ #define REG_CR … /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/ #define REG_CR_BASICCAN_INITIAL … #define REG_CR_BASICCAN_INITIAL_MASK … #define REG_SR_BASICCAN_INITIAL … #define REG_IR_BASICCAN_INITIAL … /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/ #define REG_MOD_PELICAN_INITIAL … #define REG_SR_PELICAN_INITIAL … #define REG_IR_PELICAN_INITIAL … #define ADLINK_PCI_VENDOR_ID … #define ADLINK_PCI_DEVICE_ID … #define ESD_PCI_SUB_SYS_ID_PCI200 … #define ESD_PCI_SUB_SYS_ID_PCI266 … #define ESD_PCI_SUB_SYS_ID_PMC266 … #define ESD_PCI_SUB_SYS_ID_CPCI200 … #define ESD_PCI_SUB_SYS_ID_PCIE2000 … #define ESD_PCI_SUB_SYS_ID_PCI104200 … #define CAN200PCI_DEVICE_ID … #define CAN200PCI_VENDOR_ID … #define CAN200PCI_SUB_DEVICE_ID … #define CAN200PCI_SUB_VENDOR_ID … #define IXXAT_PCI_VENDOR_ID … #define IXXAT_PCI_DEVICE_ID … #define IXXAT_PCI_SUB_SYS_ID … #define MARATHON_PCI_DEVICE_ID … #define MARATHON_PCIE_DEVICE_ID … #define TEWS_PCI_VENDOR_ID … #define TEWS_PCI_DEVICE_ID_TMPC810 … #define CTI_PCI_DEVICE_ID_CRG001 … #define MOXA_PCI_VENDOR_ID … #define MOXA_PCI_DEVICE_ID … #define ASEM_RAW_CAN_VENDOR_ID … #define ASEM_RAW_CAN_DEVICE_ID … #define ASEM_RAW_CAN_SUB_VENDOR_ID … #define ASEM_RAW_CAN_SUB_DEVICE_ID … #define ASEM_RAW_CAN_SUB_DEVICE_ID_BIS … #define ASEM_RAW_CAN_RST_REGISTER … #define ASEM_RAW_CAN_RST_MASK_CAN1 … #define ASEM_RAW_CAN_RST_MASK_CAN2 … static void plx_pci_reset_common(struct pci_dev *pdev); static void plx9056_pci_reset_common(struct pci_dev *pdev); static void plx_pci_reset_marathon_pci(struct pci_dev *pdev); static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev); static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev); struct plx_pci_channel_map { … }; struct plx_pci_card_info { … }; static struct plx_pci_card_info plx_pci_card_info_adlink = …; static struct plx_pci_card_info plx_pci_card_info_adlink_se = …; static struct plx_pci_card_info plx_pci_card_info_esd200 = …; static struct plx_pci_card_info plx_pci_card_info_esd266 = …; static struct plx_pci_card_info plx_pci_card_info_esd2000 = …; static struct plx_pci_card_info plx_pci_card_info_ixxat = …; static struct plx_pci_card_info plx_pci_card_info_marathon_pci = …; static struct plx_pci_card_info plx_pci_card_info_marathon_pcie = …; static struct plx_pci_card_info plx_pci_card_info_tews = …; static struct plx_pci_card_info plx_pci_card_info_cti = …; static struct plx_pci_card_info plx_pci_card_info_elcus = …; static struct plx_pci_card_info plx_pci_card_info_moxa = …; static struct plx_pci_card_info plx_pci_card_info_asem_dual_can = …; static const struct pci_device_id plx_pci_tbl[] = …; MODULE_DEVICE_TABLE(pci, plx_pci_tbl); static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port) { … } static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val) { … } /* * Check if a CAN controller is present at the specified location * by trying to switch 'em from the Basic mode into the PeliCAN mode. * Also check states of some registers in reset mode. */ static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) { … } /* * PLX9030/50/52 software reset * Also LRESET# asserts and brings to reset device on the Local Bus (if wired). * For most cards it's enough for reset the SJA1000 chips. */ static void plx_pci_reset_common(struct pci_dev *pdev) { struct plx_pci_card *card = pci_get_drvdata(pdev); u32 cntrl; cntrl = ioread32(card->conf_addr + PLX_CNTRL); cntrl |= PLX_PCI_RESET; iowrite32(cntrl, card->conf_addr + PLX_CNTRL); udelay(100); cntrl ^= PLX_PCI_RESET; iowrite32(cntrl, card->conf_addr + PLX_CNTRL); }; /* * PLX9056 software reset * Assert LRESET# and reset device(s) on the Local Bus (if wired). */ static void plx9056_pci_reset_common(struct pci_dev *pdev) { struct plx_pci_card *card = pci_get_drvdata(pdev); u32 cntrl; /* issue a local bus reset */ cntrl = ioread32(card->conf_addr + PLX9056_CNTRL); cntrl |= PLX_PCI_RESET; iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); udelay(100); cntrl ^= PLX_PCI_RESET; iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); /* reload local configuration from EEPROM */ cntrl |= PLX9056_PCI_RCR; iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); /* * There is no safe way to poll for the end * of reconfiguration process. Waiting for 10ms * is safe. */ mdelay(10); cntrl ^= PLX9056_PCI_RCR; iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); }; /* Special reset function for Marathon CAN-bus-PCI card */ static void plx_pci_reset_marathon_pci(struct pci_dev *pdev) { … } /* Special reset function for Marathon CAN-bus-PCIe card */ static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev) { … } /* Special reset function for ASEM Dual CAN raw card */ static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev) { … } static void plx_pci_del_card(struct pci_dev *pdev) { … } /* * Probe PLX90xx based device for the SJA1000 chips and register each * available CAN channel to SJA1000 Socket-CAN subsystem. */ static int plx_pci_add_card(struct pci_dev *pdev, const struct pci_device_id *ent) { … } static struct pci_driver plx_pci_driver = …; module_pci_driver(…) …;
Codebase Browser
linux