linux/drivers/net/dsa/hirschmann/hellcreek.h

/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
 * DSA driver for:
 * Hirschmann Hellcreek TSN switch.
 *
 * Copyright (C) 2019-2021 Linutronix GmbH
 * Author Kurt Kanzenbach <[email protected]>
 */

#ifndef _HELLCREEK_H_
#define _HELLCREEK_H_

#include <linux/bitmap.h>
#include <linux/bitops.h>
#include <linux/container_of.h>
#include <linux/device.h>
#include <linux/leds.h>
#include <linux/mutex.h>
#include <linux/platform_data/hirschmann-hellcreek.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/timecounter.h>
#include <linux/types.h>
#include <linux/workqueue.h>

#include <net/dsa.h>
#include <net/pkt_sched.h>

/* Ports:
 *  - 0: CPU
 *  - 1: Tunnel
 *  - 2: TSN front port 1
 *  - 3: TSN front port 2
 *  - ...
 */
#define CPU_PORT
#define TUNNEL_PORT

#define HELLCREEK_VLAN_NO_MEMBER
#define HELLCREEK_VLAN_UNTAGGED_MEMBER
#define HELLCREEK_VLAN_TAGGED_MEMBER
#define HELLCREEK_NUM_EGRESS_QUEUES
#define HELLCREEK_DEFAULT_MAX_SDU

/* Register definitions */
#define HR_MODID_C
#define HR_REL_L_C
#define HR_REL_H_C
#define HR_BLD_L_C
#define HR_BLD_H_C
#define HR_CTRL_C
#define HR_CTRL_C_READY
#define HR_CTRL_C_TRANSITION
#define HR_CTRL_C_ENABLE

#define HR_PSEL
#define HR_PSEL_PTWSEL_SHIFT
#define HR_PSEL_PTWSEL_MASK
#define HR_PSEL_PRTCWSEL_SHIFT
#define HR_PSEL_PRTCWSEL_MASK

#define HR_PTCFG
#define HR_PTCFG_MLIMIT_EN
#define HR_PTCFG_UMC_FLT
#define HR_PTCFG_UUC_FLT
#define HR_PTCFG_UNTRUST
#define HR_PTCFG_TAG_REQUIRED
#define HR_PTCFG_PPRIO_SHIFT
#define HR_PTCFG_PPRIO_MASK
#define HR_PTCFG_INGRESSFLT
#define HR_PTCFG_BLOCKED
#define HR_PTCFG_LEARNING_EN
#define HR_PTCFG_ADMIN_EN

#define HR_PRTCCFG
#define HR_PRTCCFG_PCP_TC_MAP_SHIFT
#define HR_PRTCCFG_PCP_TC_MAP_MASK

#define HR_PTPRTCCFG
#define HR_PTPRTCCFG_SET_QTRACK
#define HR_PTPRTCCFG_REJECT
#define HR_PTPRTCCFG_MAXSDU_SHIFT
#define HR_PTPRTCCFG_MAXSDU_MASK

#define HR_CSEL
#define HR_CSEL_SHIFT
#define HR_CSEL_MASK
#define HR_CRDL
#define HR_CRDH

#define HR_SWTRC_CFG
#define HR_SWTRC0
#define HR_SWTRC1
#define HR_PFREE
#define HR_MFREE

#define HR_FDBAGE
#define HR_FDBMAX
#define HR_FDBRDL
#define HR_FDBRDM
#define HR_FDBRDH

#define HR_FDBMDRD
#define HR_FDBMDRD_PORTMASK_SHIFT
#define HR_FDBMDRD_PORTMASK_MASK
#define HR_FDBMDRD_AGE_SHIFT
#define HR_FDBMDRD_AGE_MASK
#define HR_FDBMDRD_OBT
#define HR_FDBMDRD_PASS_BLOCKED
#define HR_FDBMDRD_STATIC
#define HR_FDBMDRD_REPRIO_TC_SHIFT
#define HR_FDBMDRD_REPRIO_TC_MASK
#define HR_FDBMDRD_REPRIO_EN

#define HR_FDBWDL
#define HR_FDBWDM
#define HR_FDBWDH
#define HR_FDBWRM0
#define HR_FDBWRM0_PORTMASK_SHIFT
#define HR_FDBWRM0_PORTMASK_MASK
#define HR_FDBWRM0_OBT
#define HR_FDBWRM0_PASS_BLOCKED
#define HR_FDBWRM0_REPRIO_TC_SHIFT
#define HR_FDBWRM0_REPRIO_TC_MASK
#define HR_FDBWRM0_REPRIO_EN
#define HR_FDBWRM1

#define HR_FDBWRCMD
#define HR_FDBWRCMD_FDBDEL

#define HR_SWCFG
#define HR_SWCFG_GM_STATEMD
#define HR_SWCFG_LAS_MODE_SHIFT
#define HR_SWCFG_LAS_MODE_MASK
#define HR_SWCFG_LAS_OFF
#define HR_SWCFG_LAS_ON
#define HR_SWCFG_LAS_STATIC
#define HR_SWCFG_CT_EN
#define HR_SWCFG_VLAN_UNAWARE
#define HR_SWCFG_ALWAYS_OBT
#define HR_SWCFG_FDBAGE_EN
#define HR_SWCFG_FDBLRN_EN

#define HR_SWSTAT
#define HR_SWSTAT_FAIL
#define HR_SWSTAT_BUSY

#define HR_SWCMD
#define HW_SWCMD_FLUSH

#define HR_VIDCFG
#define HR_VIDCFG_VID_SHIFT
#define HR_VIDCFG_VID_MASK
#define HR_VIDCFG_PVID

#define HR_VIDMBRCFG
#define HR_VIDMBRCFG_P0MBR_SHIFT
#define HR_VIDMBRCFG_P0MBR_MASK
#define HR_VIDMBRCFG_P1MBR_SHIFT
#define HR_VIDMBRCFG_P1MBR_MASK
#define HR_VIDMBRCFG_P2MBR_SHIFT
#define HR_VIDMBRCFG_P2MBR_MASK
#define HR_VIDMBRCFG_P3MBR_SHIFT
#define HR_VIDMBRCFG_P3MBR_MASK

#define HR_FEABITS0
#define HR_FEABITS0_FDBBINS_SHIFT
#define HR_FEABITS0_FDBBINS_MASK
#define HR_FEABITS0_PCNT_SHIFT
#define HR_FEABITS0_PCNT_MASK
#define HR_FEABITS0_MCNT_SHIFT
#define HR_FEABITS0_MCNT_MASK

#define TR_QTRACK
#define TR_TGDVER
#define TR_TGDVER_REV_MIN_MASK
#define TR_TGDVER_REV_MIN_SHIFT
#define TR_TGDVER_REV_MAJ_MASK
#define TR_TGDVER_REV_MAJ_SHIFT
#define TR_TGDSEL
#define TR_TGDSEL_TDGSEL_MASK
#define TR_TGDSEL_TDGSEL_SHIFT
#define TR_TGDCTRL
#define TR_TGDCTRL_GATE_EN
#define TR_TGDCTRL_CYC_SNAP
#define TR_TGDCTRL_SNAP_EST
#define TR_TGDCTRL_ADMINGATESTATES_MASK
#define TR_TGDCTRL_ADMINGATESTATES_SHIFT
#define TR_TGDSTAT0
#define TR_TGDSTAT1
#define TR_ESTWRL
#define TR_ESTWRH
#define TR_ESTCMD
#define TR_ESTCMD_ESTSEC_MASK
#define TR_ESTCMD_ESTSEC_SHIFT
#define TR_ESTCMD_ESTARM
#define TR_ESTCMD_ESTSWCFG
#define TR_EETWRL
#define TR_EETWRH
#define TR_EETCMD
#define TR_EETCMD_EETSEC_MASK
#define TR_EETCMD_EETSEC_SHIFT
#define TR_EETCMD_EETARM
#define TR_CTWRL
#define TR_CTWRH
#define TR_LCNSL
#define TR_LCNSH
#define TR_LCS
#define TR_GCLDAT
#define TR_GCLDAT_GCLWRGATES_MASK
#define TR_GCLDAT_GCLWRGATES_SHIFT
#define TR_GCLDAT_GCLWRLAST
#define TR_GCLDAT_GCLOVRI
#define TR_GCLTIL
#define TR_GCLTIH
#define TR_GCLCMD
#define TR_GCLCMD_GCLWRADR_MASK
#define TR_GCLCMD_GCLWRADR_SHIFT
#define TR_GCLCMD_INIT_GATE_STATES_MASK
#define TR_GCLCMD_INIT_GATE_STATES_SHIFT

struct hellcreek_counter {};

struct hellcreek;

/* State flags for hellcreek_port_hwtstamp::state */
enum {};

/* A structure to hold hardware timestamping information per port */
struct hellcreek_port_hwtstamp {};

struct hellcreek_port {};

struct hellcreek_fdb_entry {};

struct hellcreek {};

/* A Qbv schedule can only started up to 8 seconds in the future. If the delta
 * between the base time and the current ptp time is larger than 8 seconds, then
 * use periodic work to check for the schedule to be started. The delayed work
 * cannot be armed directly to $base_time - 8 + X, because for large deltas the
 * PTP frequency matters.
 */
#define HELLCREEK_SCHEDULE_PERIOD
#define dw_to_hellcreek_port(dw)

/* Devlink resources */
enum hellcreek_devlink_resource_id {};

struct hellcreek_devlink_vlan_entry {};

#endif /* _HELLCREEK_H_ */