linux/drivers/net/dsa/b53/b53_serdes.h

/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
 * Northstar Plus switch SerDes/SGMII PHY definitions
 *
 * Copyright (C) 2018 Florian Fainelli <[email protected]>
 */

#include <linux/phy.h>
#include <linux/types.h>

/* Non-standard page used to access SerDes PHY registers on NorthStar Plus */
#define B53_SERDES_PAGE
#define B53_SERDES_BLKADDR
#define B53_SERDES_LANE

#define B53_SERDES_ID0
#define SERDES_ID0_MODEL_MASK
#define SERDES_ID0_REV_NUM_SHIFT
#define SERDES_ID0_REV_NUM_MASK
#define SERDES_ID0_REV_LETTER_SHIFT

#define B53_SERDES_MII_REG(x)
#define B53_SERDES_DIGITAL_CONTROL(x)
#define B53_SERDES_DIGITAL_STATUS

/* SERDES_DIGITAL_CONTROL1 */
#define FIBER_MODE_1000X
#define TBI_INTERFACE
#define SIGNAL_DETECT_EN
#define INVERT_SIGNAL_DETECT
#define AUTODET_EN
#define SGMII_MASTER_MODE
#define DISABLE_DLL_PWRDOWN
#define CRC_CHECKER_DIS
#define COMMA_DET_EN
#define ZERO_COMMA_DET_EN
#define REMOTE_LOOPBACK
#define SEL_RX_PKTS_FOR_CNTR
#define MASTER_MDIO_PHY_SEL
#define DISABLE_SIGNAL_DETECT_FLT

/* SERDES_DIGITAL_CONTROL2 */
#define EN_PARALLEL_DET
#define DIS_FALSE_LINK
#define FLT_FORCE_LINK
#define EN_AUTONEG_ERR_TIMER
#define DIS_REMOTE_FAULT_SENSING
#define FORCE_XMIT_DATA
#define AUTONEG_FAST_TIMERS
#define DIS_CARRIER_EXTEND
#define DIS_TRRR_GENERATION
#define BYPASS_PCS_RX
#define BYPASS_PCS_TX
#define TEST_CNTR_EN
#define TX_PACKET_SEQ_TEST
#define TX_IDLE_JAM_SEQ_TEST
#define CLR_BER_CNTR

/* SERDES_DIGITAL_CONTROL3 */
#define TX_FIFO_RST
#define FIFO_ELAST_TX_RX_SHIFT
#define FIFO_ELAST_TX_RX_5K
#define FIFO_ELAST_TX_RX_10K
#define FIFO_ELAST_TX_RX_13_5K
#define FIFO_ELAST_TX_RX_18_5K
#define BLOCK_TXEN_MODE
#define JAM_FALSE_CARRIER_MODE
#define EXT_PHY_CRS_MODE
#define INVERT_EXT_PHY_CRS
#define DISABLE_TX_CRS

/* SERDES_DIGITAL_STATUS */
#define SGMII_MODE
#define LINK_STATUS
#define DUPLEX_STATUS
#define SPEED_STATUS_SHIFT
#define SPEED_STATUS_10
#define SPEED_STATUS_100
#define SPEED_STATUS_1000
#define SPEED_STATUS_2500
#define SPEED_STATUS_MASK
#define PAUSE_RESOLUTION_TX_SIDE
#define PAUSE_RESOLUTION_RX_SIDE
#define LINK_STATUS_CHANGE
#define EARLY_END_EXT_DET
#define CARRIER_EXT_ERR_DET
#define RX_ERR_DET
#define TX_ERR_DET
#define CRC_ERR_DET
#define FALSE_CARRIER_ERR_DET
#define RXFIFO_ERR_DET
#define TXFIFO_ERR_DET

/* Block offsets */
#define SERDES_DIGITAL_BLK
#define SERDES_ID0
#define SERDES_MII_BLK
#define SERDES_XGXSBLK0_BLOCKADDRESS

struct phylink_link_state;

static inline u8 b53_serdes_map_lane(struct b53_device *dev, int port)
{}

void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
			 phy_interface_t interface, bool link_up);
struct phylink_pcs *b53_serdes_phylink_mac_select_pcs(struct b53_device *dev,
						      int port,
						      phy_interface_t interface);
void b53_serdes_phylink_get_caps(struct b53_device *dev, int port,
				 struct phylink_config *config);
#if IS_ENABLED(CONFIG_B53_SERDES)
int b53_serdes_init(struct b53_device *dev, int port);
#else
static inline int b53_serdes_init(struct b53_device *dev, int port)
{
	return -ENODEV;
}
#endif