/* SPDX-License-Identifier: GPL-2.0 */ /* * Microchip KSZ9477 register definitions * * Copyright (C) 2017-2018 Microchip Technology Inc. */ #ifndef __KSZ9477_REGS_H #define __KSZ9477_REGS_H #define KS_PRIO_M … #define KS_PRIO_S … /* 0 - Operation */ #define REG_CHIP_ID0__1 … #define REG_CHIP_ID1__1 … #define FAMILY_ID … #define FAMILY_ID_94 … #define FAMILY_ID_95 … #define FAMILY_ID_85 … #define FAMILY_ID_98 … #define FAMILY_ID_88 … #define REG_CHIP_ID2__1 … #define CHIP_ID_66 … #define CHIP_ID_67 … #define CHIP_ID_77 … #define CHIP_ID_93 … #define CHIP_ID_96 … #define CHIP_ID_97 … #define REG_CHIP_ID3__1 … #define SWITCH_REVISION_M … #define SWITCH_REVISION_S … #define SWITCH_RESET … #define REG_SW_PME_CTRL … #define PME_ENABLE … #define PME_POLARITY … #define REG_GLOBAL_OPTIONS … #define SW_GIGABIT_ABLE … #define SW_REDUNDANCY_ABLE … #define SW_AVB_ABLE … #define SW_9567_RL_5_2 … #define SW_9477_SL_5_2 … #define SW_9896_GL_5_1 … #define SW_9896_RL_5_1 … #define SW_9896_SL_5_1 … #define SW_9895_GL_4_1 … #define SW_9895_RL_4_1 … #define SW_9895_SL_4_1 … #define SW_9896_RL_4_2 … #define SW_9893_RL_2_1 … #define SW_9893_SL_2_1 … #define SW_9893_GL_2_1 … #define SW_QW_ABLE … #define SW_9893_RN_2_1 … #define REG_SW_INT_STATUS__4 … #define REG_SW_INT_MASK__4 … #define LUE_INT … #define TRIG_TS_INT … #define APB_TIMEOUT_INT … #define SWITCH_INT_MASK … #define REG_SW_PORT_INT_STATUS__4 … #define REG_SW_PORT_INT_MASK__4 … #define REG_SW_PHY_INT_STATUS … #define REG_SW_PHY_INT_ENABLE … /* 1 - Global */ #define REG_SW_GLOBAL_SERIAL_CTRL_0 … #define SW_SPARE_REG_2 … #define SW_SPARE_REG_1 … #define SW_SPARE_REG_0 … #define SW_BIG_ENDIAN … #define SPI_AUTO_EDGE_DETECTION … #define SPI_CLOCK_OUT_RISING_EDGE … #define REG_SW_GLOBAL_OUTPUT_CTRL__1 … #define SW_ENABLE_REFCLKO … #define SW_REFCLKO_IS_125MHZ … #define REG_SW_IBA__4 … #define SW_IBA_ENABLE … #define SW_IBA_DA_MATCH … #define SW_IBA_INIT … #define SW_IBA_QID_M … #define SW_IBA_QID_S … #define SW_IBA_PORT_M … #define SW_IBA_PORT_S … #define SW_IBA_FRAME_TPID_M … #define REG_SW_APB_TIMEOUT_ADDR__4 … #define APB_TIMEOUT_ACKNOWLEDGE … #define REG_SW_IBA_SYNC__1 … #define REG_SW_IBA_STATUS__4 … #define SW_IBA_REQ … #define SW_IBA_RESP … #define SW_IBA_DA_MISMATCH … #define SW_IBA_FMT_MISMATCH … #define SW_IBA_CODE_ERROR … #define SW_IBA_CMD_ERROR … #define SW_IBA_CMD_LOC_M … #define REG_SW_IBA_STATES__4 … #define SW_IBA_BUF_STATE_S … #define SW_IBA_CMD_STATE_S … #define SW_IBA_RESP_STATE_S … #define SW_IBA_STATE_M … #define SW_IBA_PACKET_SIZE_M … #define SW_IBA_PACKET_SIZE_S … #define SW_IBA_FMT_ID_M … #define REG_SW_IBA_RESULT__4 … #define SW_IBA_SIZE_S … #define SW_IBA_RETRY_CNT_M … /* 2 - PHY */ #define REG_SW_POWER_MANAGEMENT_CTRL … #define SW_PLL_POWER_DOWN … #define SW_POWER_DOWN_MODE … #define SW_ENERGY_DETECTION … #define SW_SOFT_POWER_DOWN … #define SW_POWER_SAVING … /* 3 - Operation Control */ #define REG_SW_OPERATION … #define SW_DOUBLE_TAG … #define SW_RESET … #define REG_SW_MTU__2 … #define REG_SW_MTU_MASK … #define REG_SW_ISP_TPID__2 … #define REG_SW_HSR_TPID__2 … #define REG_AVB_STRATEGY__2 … #define SW_SHAPING_CREDIT_ACCT … #define SW_POLICING_CREDIT_ACCT … #define REG_SW_LUE_CTRL_0 … #define SW_VLAN_ENABLE … #define SW_DROP_INVALID_VID … #define SW_AGE_CNT_M … #define SW_AGE_CNT_S … #define SW_AGE_PERIOD_10_8_M … #define SW_RESV_MCAST_ENABLE … #define SW_HASH_OPTION_M … #define SW_HASH_OPTION_CRC … #define SW_HASH_OPTION_XOR … #define SW_HASH_OPTION_DIRECT … #define REG_SW_LUE_CTRL_1 … #define UNICAST_LEARN_DISABLE … #define SW_SRC_ADDR_FILTER … #define SW_FLUSH_STP_TABLE … #define SW_FLUSH_MSTP_TABLE … #define SW_FWD_MCAST_SRC_ADDR … #define SW_AGING_ENABLE … #define SW_FAST_AGING … #define SW_LINK_AUTO_AGING … #define REG_SW_LUE_CTRL_2 … #define SW_TRAP_DOUBLE_TAG … #define SW_EGRESS_VLAN_FILTER_DYN … #define SW_EGRESS_VLAN_FILTER_STA … #define SW_FLUSH_OPTION_M … #define SW_FLUSH_OPTION_S … #define SW_FLUSH_OPTION_DYN_MAC … #define SW_FLUSH_OPTION_STA_MAC … #define SW_FLUSH_OPTION_BOTH … #define SW_PRIO_M … #define SW_PRIO_DA … #define SW_PRIO_SA … #define SW_PRIO_HIGHEST_DA_SA … #define SW_PRIO_LOWEST_DA_SA … #define REG_SW_LUE_CTRL_3 … #define SW_AGE_PERIOD_7_0_M … #define REG_SW_LUE_INT_STATUS … #define REG_SW_LUE_INT_ENABLE … #define LEARN_FAIL_INT … #define ALMOST_FULL_INT … #define WRITE_FAIL_INT … #define REG_SW_LUE_INDEX_0__2 … #define ENTRY_INDEX_M … #define REG_SW_LUE_INDEX_1__2 … #define FAIL_INDEX_M … #define REG_SW_LUE_INDEX_2__2 … #define REG_SW_LUE_UNK_UCAST_CTRL__4 … #define SW_UNK_UCAST_ENABLE … #define REG_SW_LUE_UNK_MCAST_CTRL__4 … #define SW_UNK_MCAST_ENABLE … #define REG_SW_LUE_UNK_VID_CTRL__4 … #define SW_UNK_VID_ENABLE … #define REG_SW_MAC_CTRL_0 … #define SW_NEW_BACKOFF … #define SW_CHECK_LENGTH … #define SW_PAUSE_UNH_MODE … #define SW_AGGR_BACKOFF … #define REG_SW_MAC_CTRL_1 … #define SW_BACK_PRESSURE … #define SW_BACK_PRESSURE_COLLISION … #define FAIR_FLOW_CTRL … #define NO_EXC_COLLISION_DROP … #define SW_JUMBO_PACKET … #define SW_LEGAL_PACKET_DISABLE … #define SW_PASS_SHORT_FRAME … #define REG_SW_MAC_CTRL_2 … #define SW_REPLACE_VID … #define REG_SW_MAC_CTRL_3 … #define REG_SW_MAC_CTRL_4 … #define SW_PASS_PAUSE … #define REG_SW_MAC_CTRL_5 … #define SW_OUT_RATE_LIMIT_QUEUE_BASED … #define REG_SW_MAC_CTRL_6 … #define SW_MIB_COUNTER_FLUSH … #define SW_MIB_COUNTER_FREEZE … #define REG_SW_MAC_802_1P_MAP_0 … #define REG_SW_MAC_802_1P_MAP_1 … #define REG_SW_MAC_802_1P_MAP_2 … #define REG_SW_MAC_802_1P_MAP_3 … #define SW_802_1P_MAP_M … #define SW_802_1P_MAP_S … #define REG_SW_MAC_ISP_CTRL … #define REG_SW_MAC_TOS_CTRL … #define SW_TOS_DSCP_REMARK … #define SW_TOS_DSCP_REMAP … #define REG_SW_MAC_TOS_PRIO_0 … #define REG_SW_MAC_TOS_PRIO_1 … #define REG_SW_MAC_TOS_PRIO_2 … #define REG_SW_MAC_TOS_PRIO_3 … #define REG_SW_MAC_TOS_PRIO_4 … #define REG_SW_MAC_TOS_PRIO_5 … #define REG_SW_MAC_TOS_PRIO_6 … #define REG_SW_MAC_TOS_PRIO_7 … #define REG_SW_MAC_TOS_PRIO_8 … #define REG_SW_MAC_TOS_PRIO_9 … #define REG_SW_MAC_TOS_PRIO_10 … #define REG_SW_MAC_TOS_PRIO_11 … #define REG_SW_MAC_TOS_PRIO_12 … #define REG_SW_MAC_TOS_PRIO_13 … #define REG_SW_MAC_TOS_PRIO_14 … #define REG_SW_MAC_TOS_PRIO_15 … #define REG_SW_MAC_TOS_PRIO_16 … #define REG_SW_MAC_TOS_PRIO_17 … #define REG_SW_MAC_TOS_PRIO_18 … #define REG_SW_MAC_TOS_PRIO_19 … #define REG_SW_MAC_TOS_PRIO_20 … #define REG_SW_MAC_TOS_PRIO_21 … #define REG_SW_MAC_TOS_PRIO_22 … #define REG_SW_MAC_TOS_PRIO_23 … #define REG_SW_MAC_TOS_PRIO_24 … #define REG_SW_MAC_TOS_PRIO_25 … #define REG_SW_MAC_TOS_PRIO_26 … #define REG_SW_MAC_TOS_PRIO_27 … #define REG_SW_MAC_TOS_PRIO_28 … #define REG_SW_MAC_TOS_PRIO_29 … #define REG_SW_MAC_TOS_PRIO_30 … #define REG_SW_MAC_TOS_PRIO_31 … #define REG_SW_MRI_CTRL_0 … #define SW_IGMP_SNOOP … #define SW_IPV6_MLD_OPTION … #define SW_IPV6_MLD_SNOOP … #define SW_MIRROR_RX_TX … #define REG_SW_CLASS_D_IP_CTRL__4 … #define SW_CLASS_D_IP_ENABLE … #define REG_SW_MRI_CTRL_8 … #define SW_NO_COLOR_S … #define SW_RED_COLOR_S … #define SW_YELLOW_COLOR_S … #define SW_GREEN_COLOR_S … #define SW_COLOR_M … #define REG_SW_QM_CTRL__4 … #define PRIO_SCHEME_SELECT_M … #define PRIO_SCHEME_SELECT_S … #define PRIO_MAP_3_HI … #define PRIO_MAP_2_HI … #define PRIO_MAP_0_LO … #define UNICAST_VLAN_BOUNDARY … #define REG_SW_EEE_QM_CTRL__2 … #define REG_SW_EEE_TXQ_WAIT_TIME__2 … /* 4 - */ #define REG_SW_VLAN_ENTRY__4 … #define VLAN_VALID … #define VLAN_FORWARD_OPTION … #define VLAN_PRIO_M … #define VLAN_PRIO_S … #define VLAN_MSTP_M … #define VLAN_MSTP_S … #define VLAN_FID_M … #define REG_SW_VLAN_ENTRY_UNTAG__4 … #define REG_SW_VLAN_ENTRY_PORTS__4 … #define REG_SW_VLAN_ENTRY_INDEX__2 … #define VLAN_INDEX_M … #define REG_SW_VLAN_CTRL … #define VLAN_START … #define VLAN_ACTION … #define VLAN_WRITE … #define VLAN_READ … #define VLAN_CLEAR … #define REG_SW_ALU_INDEX_0 … #define ALU_FID_INDEX_S … #define ALU_MAC_ADDR_HI … #define REG_SW_ALU_INDEX_1 … #define ALU_DIRECT_INDEX_M … #define REG_SW_ALU_CTRL__4 … #define ALU_VALID_CNT_M … #define ALU_VALID_CNT_S … #define ALU_START … #define ALU_VALID … #define ALU_DIRECT … #define ALU_ACTION … #define ALU_WRITE … #define ALU_READ … #define ALU_SEARCH … #define REG_SW_ALU_STAT_CTRL__4 … #define ALU_RESV_MCAST_INDEX_M … #define ALU_STAT_START … #define ALU_RESV_MCAST_ADDR … #define REG_SW_ALU_VAL_A … #define ALU_V_STATIC_VALID … #define ALU_V_SRC_FILTER … #define ALU_V_DST_FILTER … #define ALU_V_PRIO_AGE_CNT_M … #define ALU_V_PRIO_AGE_CNT_S … #define ALU_V_MSTP_M … #define REG_SW_ALU_VAL_B … #define ALU_V_OVERRIDE … #define ALU_V_USE_FID … #define ALU_V_PORT_MAP … #define REG_SW_ALU_VAL_C … #define ALU_V_FID_M … #define ALU_V_FID_S … #define ALU_V_MAC_ADDR_HI … #define REG_SW_ALU_VAL_D … #define REG_HSR_ALU_INDEX_0 … #define REG_HSR_ALU_INDEX_1 … #define HSR_DST_MAC_INDEX_LO_S … #define HSR_SRC_MAC_INDEX_HI … #define REG_HSR_ALU_INDEX_2 … #define HSR_INDEX_MAX … #define HSR_DIRECT_INDEX_M … #define REG_HSR_ALU_INDEX_3 … #define HSR_PATH_INDEX_M … #define REG_HSR_ALU_CTRL__4 … #define HSR_VALID_CNT_M … #define HSR_VALID_CNT_S … #define HSR_START … #define HSR_VALID … #define HSR_SEARCH_END … #define HSR_DIRECT … #define HSR_ACTION … #define HSR_WRITE … #define HSR_READ … #define HSR_SEARCH … #define REG_HSR_ALU_VAL_A … #define HSR_V_STATIC_VALID … #define HSR_V_AGE_CNT_M … #define HSR_V_AGE_CNT_S … #define HSR_V_PATH_ID_M … #define REG_HSR_ALU_VAL_B … #define REG_HSR_ALU_VAL_C … #define HSR_V_DST_MAC_ADDR_LO_S … #define HSR_V_SRC_MAC_ADDR_HI … #define REG_HSR_ALU_VAL_D … #define REG_HSR_ALU_VAL_E … #define HSR_V_START_SEQ_1_S … #define HSR_V_START_SEQ_2_S … #define REG_HSR_ALU_VAL_F … #define HSR_V_EXP_SEQ_1_S … #define HSR_V_EXP_SEQ_2_S … #define REG_HSR_ALU_VAL_G … #define HSR_V_SEQ_CNT_1_S … #define HSR_V_SEQ_CNT_2_S … #define HSR_V_SEQ_M … /* 5 - PTP Clock */ #define REG_PTP_CLK_CTRL … #define PTP_STEP_ADJ … #define PTP_STEP_DIR … #define PTP_READ_TIME … #define PTP_LOAD_TIME … #define PTP_CLK_ADJ_ENABLE … #define PTP_CLK_ENABLE … #define PTP_CLK_RESET … #define REG_PTP_RTC_SUB_NANOSEC__2 … #define PTP_RTC_SUB_NANOSEC_M … #define REG_PTP_RTC_NANOSEC … #define REG_PTP_RTC_NANOSEC_H … #define REG_PTP_RTC_NANOSEC_L … #define REG_PTP_RTC_SEC … #define REG_PTP_RTC_SEC_H … #define REG_PTP_RTC_SEC_L … #define REG_PTP_SUBNANOSEC_RATE … #define REG_PTP_SUBNANOSEC_RATE_H … #define PTP_RATE_DIR … #define PTP_TMP_RATE_ENABLE … #define REG_PTP_SUBNANOSEC_RATE_L … #define REG_PTP_RATE_DURATION … #define REG_PTP_RATE_DURATION_H … #define REG_PTP_RATE_DURATION_L … #define REG_PTP_MSG_CONF1 … #define PTP_802_1AS … #define PTP_ENABLE … #define PTP_ETH_ENABLE … #define PTP_IPV4_UDP_ENABLE … #define PTP_IPV6_UDP_ENABLE … #define PTP_TC_P2P … #define PTP_MASTER … #define PTP_1STEP … #define REG_PTP_MSG_CONF2 … #define PTP_UNICAST_ENABLE … #define PTP_ALTERNATE_MASTER … #define PTP_ALL_HIGH_PRIO … #define PTP_SYNC_CHECK … #define PTP_DELAY_CHECK … #define PTP_PDELAY_CHECK … #define PTP_DROP_SYNC_DELAY_REQ … #define PTP_DOMAIN_CHECK … #define PTP_UDP_CHECKSUM … #define REG_PTP_DOMAIN_VERSION … #define PTP_VERSION_M … #define PTP_DOMAIN_M … #define REG_PTP_UNIT_INDEX__4 … #define PTP_UNIT_M … #define PTP_GPIO_INDEX_S … #define PTP_TSI_INDEX_S … #define PTP_TOU_INDEX_S … #define REG_PTP_TRIG_STATUS__4 … #define TRIG_ERROR_S … #define TRIG_DONE_S … #define REG_PTP_INT_STATUS__4 … #define TRIG_INT_S … #define TS_INT_S … #define TRIG_UNIT_M … #define TS_UNIT_M … #define REG_PTP_CTRL_STAT__4 … #define GPIO_IN … #define GPIO_OUT … #define TS_INT_ENABLE … #define TRIG_ACTIVE … #define TRIG_ENABLE … #define TRIG_RESET … #define TS_ENABLE … #define TS_RESET … #define GPIO_CTRL_M … #define TRIG_CTRL_M … #define TS_CTRL_M … #define REG_TRIG_TARGET_NANOSEC … #define REG_TRIG_TARGET_SEC … #define REG_TRIG_CTRL__4 … #define TRIG_CASCADE_ENABLE … #define TRIG_CASCADE_TAIL … #define TRIG_CASCADE_UPS_M … #define TRIG_CASCADE_UPS_S … #define TRIG_NOW … #define TRIG_NOTIFY … #define TRIG_EDGE … #define TRIG_PATTERN_S … #define TRIG_PATTERN_M … #define TRIG_NEG_EDGE … #define TRIG_POS_EDGE … #define TRIG_NEG_PULSE … #define TRIG_POS_PULSE … #define TRIG_NEG_PERIOD … #define TRIG_POS_PERIOD … #define TRIG_REG_OUTPUT … #define TRIG_GPO_S … #define TRIG_GPO_M … #define TRIG_CASCADE_ITERATE_CNT_M … #define REG_TRIG_CYCLE_WIDTH … #define REG_TRIG_CYCLE_CNT … #define TRIG_CYCLE_CNT_M … #define TRIG_CYCLE_CNT_S … #define TRIG_BIT_PATTERN_M … #define REG_TRIG_ITERATE_TIME … #define REG_TRIG_PULSE_WIDTH__4 … #define TRIG_PULSE_WIDTH_M … #define REG_TS_CTRL_STAT__4 … #define TS_EVENT_DETECT_M … #define TS_EVENT_DETECT_S … #define TS_EVENT_OVERFLOW … #define TS_GPI_M … #define TS_GPI_S … #define TS_DETECT_RISE … #define TS_DETECT_FALL … #define TS_DETECT_S … #define TS_CASCADE_TAIL … #define TS_CASCADE_UPS_M … #define TS_CASCADE_UPS_S … #define TS_CASCADE_ENABLE … #define DETECT_RISE … #define DETECT_FALL … #define REG_TS_EVENT_0_NANOSEC … #define REG_TS_EVENT_0_SEC … #define REG_TS_EVENT_0_SUB_NANOSEC … #define REG_TS_EVENT_1_NANOSEC … #define REG_TS_EVENT_1_SEC … #define REG_TS_EVENT_1_SUB_NANOSEC … #define REG_TS_EVENT_2_NANOSEC … #define REG_TS_EVENT_2_SEC … #define REG_TS_EVENT_2_SUB_NANOSEC … #define REG_TS_EVENT_3_NANOSEC … #define REG_TS_EVENT_3_SEC … #define REG_TS_EVENT_3_SUB_NANOSEC … #define REG_TS_EVENT_4_NANOSEC … #define REG_TS_EVENT_4_SEC … #define REG_TS_EVENT_4_SUB_NANOSEC … #define REG_TS_EVENT_5_NANOSEC … #define REG_TS_EVENT_5_SEC … #define REG_TS_EVENT_5_SUB_NANOSEC … #define REG_TS_EVENT_6_NANOSEC … #define REG_TS_EVENT_6_SEC … #define REG_TS_EVENT_6_SUB_NANOSEC … #define REG_TS_EVENT_7_NANOSEC … #define REG_TS_EVENT_7_SEC … #define REG_TS_EVENT_7_SUB_NANOSEC … #define TS_EVENT_EDGE_M … #define TS_EVENT_EDGE_S … #define TS_EVENT_NANOSEC_M … #define TS_EVENT_SUB_NANOSEC_M … #define TS_EVENT_SAMPLE … #define PORT_CTRL_ADDR(port, addr) … #define REG_GLOBAL_RR_INDEX__1 … /* DLR */ #define REG_DLR_SRC_PORT__4 … #define DLR_SRC_PORT_UNICAST … #define DLR_SRC_PORT_M … #define DLR_SRC_PORT_BOTH … #define DLR_SRC_PORT_EACH … #define REG_DLR_IP_ADDR__4 … #define REG_DLR_CTRL__1 … #define DLR_RESET_SEQ_ID … #define DLR_BACKUP_AUTO_ON … #define DLR_BEACON_TX_ENABLE … #define DLR_ASSIST_ENABLE … #define REG_DLR_STATE__1 … #define DLR_NODE_STATE_M … #define DLR_NODE_STATE_S … #define DLR_NODE_STATE_IDLE … #define DLR_NODE_STATE_FAULT … #define DLR_NODE_STATE_NORMAL … #define DLR_RING_STATE_FAULT … #define DLR_RING_STATE_NORMAL … #define REG_DLR_PRECEDENCE__1 … #define REG_DLR_BEACON_INTERVAL__4 … #define REG_DLR_BEACON_TIMEOUT__4 … #define REG_DLR_TIMEOUT_WINDOW__4 … #define DLR_TIMEOUT_WINDOW_M … #define REG_DLR_VLAN_ID__2 … #define DLR_VLAN_ID_M … #define REG_DLR_DEST_ADDR_0 … #define REG_DLR_DEST_ADDR_1 … #define REG_DLR_DEST_ADDR_2 … #define REG_DLR_DEST_ADDR_3 … #define REG_DLR_DEST_ADDR_4 … #define REG_DLR_DEST_ADDR_5 … #define REG_DLR_PORT_MAP__4 … #define REG_DLR_CLASS__1 … #define DLR_FRAME_QID_M … /* HSR */ #define REG_HSR_PORT_MAP__4 … #define REG_HSR_ALU_CTRL_0__1 … #define HSR_DUPLICATE_DISCARD … #define HSR_NODE_UNICAST … #define HSR_AGE_CNT_DEFAULT_M … #define HSR_AGE_CNT_DEFAULT_S … #define HSR_LEARN_MCAST_DISABLE … #define HSR_HASH_OPTION_M … #define HSR_HASH_DISABLE … #define HSR_HASH_UPPER_BITS … #define HSR_HASH_LOWER_BITS … #define HSR_HASH_XOR_BOTH_BITS … #define REG_HSR_ALU_CTRL_1__1 … #define HSR_LEARN_UCAST_DISABLE … #define HSR_FLUSH_TABLE … #define HSR_PROC_MCAST_SRC … #define HSR_AGING_ENABLE … #define REG_HSR_ALU_CTRL_2__2 … #define REG_HSR_ALU_AGE_PERIOD__4 … #define REG_HSR_ALU_INT_STATUS__1 … #define REG_HSR_ALU_INT_MASK__1 … #define HSR_WINDOW_OVERFLOW_INT … #define HSR_LEARN_FAIL_INT … #define HSR_ALMOST_FULL_INT … #define HSR_WRITE_FAIL_INT … #define REG_HSR_ALU_ENTRY_0__2 … #define HSR_ENTRY_INDEX_M … #define HSR_FAIL_INDEX_M … #define REG_HSR_ALU_ENTRY_1__2 … #define HSR_FAIL_LEARN_INDEX_M … #define REG_HSR_ALU_ENTRY_3__2 … #define HSR_CPU_ACCESS_ENTRY_INDEX_M … /* 0 - Operation */ #define REG_PORT_DEFAULT_VID … #define REG_PORT_CUSTOM_VID … #define REG_PORT_AVB_SR_1_VID … #define REG_PORT_AVB_SR_2_VID … #define REG_PORT_AVB_SR_1_TYPE … #define REG_PORT_AVB_SR_2_TYPE … #define REG_PORT_PME_STATUS … #define REG_PORT_PME_CTRL … #define PME_WOL_MAGICPKT … #define PME_WOL_LINKUP … #define PME_WOL_ENERGY … #define REG_PORT_INT_STATUS … #define REG_PORT_INT_MASK … #define PORT_SGMII_INT … #define PORT_PTP_INT … #define PORT_PHY_INT … #define PORT_ACL_INT … #define PORT_INT_MASK … #define REG_PORT_CTRL_0 … #define PORT_MAC_LOOPBACK … #define PORT_FORCE_TX_FLOW_CTRL … #define PORT_FORCE_RX_FLOW_CTRL … #define PORT_TAIL_TAG_ENABLE … #define PORT_QUEUE_SPLIT_MASK … #define PORT_EIGHT_QUEUE … #define PORT_FOUR_QUEUE … #define PORT_TWO_QUEUE … #define PORT_SINGLE_QUEUE … #define REG_PORT_CTRL_1 … #define PORT_SRP_ENABLE … #define REG_PORT_STATUS_0 … #define PORT_INTF_SPEED_MASK … #define PORT_INTF_SPEED_NONE … #define PORT_INTF_FULL_DUPLEX … #define PORT_TX_FLOW_CTRL … #define PORT_RX_FLOW_CTRL … #define REG_PORT_STATUS_1 … /* 1 - PHY */ #define REG_PORT_PHY_CTRL … #define PORT_PHY_RESET … #define PORT_PHY_LOOPBACK … #define PORT_SPEED_100MBIT … #define PORT_AUTO_NEG_ENABLE … #define PORT_POWER_DOWN … #define PORT_ISOLATE … #define PORT_AUTO_NEG_RESTART … #define PORT_FULL_DUPLEX … #define PORT_COLLISION_TEST … #define PORT_SPEED_1000MBIT … #define REG_PORT_PHY_STATUS … #define PORT_100BT4_CAPABLE … #define PORT_100BTX_FD_CAPABLE … #define PORT_100BTX_CAPABLE … #define PORT_10BT_FD_CAPABLE … #define PORT_10BT_CAPABLE … #define PORT_EXTENDED_STATUS … #define PORT_MII_SUPPRESS_CAPABLE … #define PORT_AUTO_NEG_ACKNOWLEDGE … #define PORT_REMOTE_FAULT … #define PORT_AUTO_NEG_CAPABLE … #define PORT_LINK_STATUS … #define PORT_JABBER_DETECT … #define PORT_EXTENDED_CAPABILITY … #define REG_PORT_PHY_ID_HI … #define REG_PORT_PHY_ID_LO … #define KSZ9477_ID_HI … #define KSZ9477_ID_LO … #define REG_PORT_PHY_AUTO_NEGOTIATION … #define PORT_AUTO_NEG_NEXT_PAGE … #define PORT_AUTO_NEG_REMOTE_FAULT … #define PORT_AUTO_NEG_ASYM_PAUSE … #define PORT_AUTO_NEG_SYM_PAUSE … #define PORT_AUTO_NEG_100BT4 … #define PORT_AUTO_NEG_100BTX_FD … #define PORT_AUTO_NEG_100BTX … #define PORT_AUTO_NEG_10BT_FD … #define PORT_AUTO_NEG_10BT … #define PORT_AUTO_NEG_SELECTOR … #define PORT_AUTO_NEG_802_3 … #define PORT_AUTO_NEG_PAUSE … #define REG_PORT_PHY_REMOTE_CAPABILITY … #define PORT_REMOTE_NEXT_PAGE … #define PORT_REMOTE_ACKNOWLEDGE … #define PORT_REMOTE_REMOTE_FAULT … #define PORT_REMOTE_ASYM_PAUSE … #define PORT_REMOTE_SYM_PAUSE … #define PORT_REMOTE_100BTX_FD … #define PORT_REMOTE_100BTX … #define PORT_REMOTE_10BT_FD … #define PORT_REMOTE_10BT … #define REG_PORT_PHY_1000_CTRL … #define PORT_AUTO_NEG_MANUAL … #define PORT_AUTO_NEG_MASTER … #define PORT_AUTO_NEG_MASTER_PREFERRED … #define PORT_AUTO_NEG_1000BT_FD … #define PORT_AUTO_NEG_1000BT … #define REG_PORT_PHY_1000_STATUS … #define PORT_MASTER_FAULT … #define PORT_LOCAL_MASTER … #define PORT_LOCAL_RX_OK … #define PORT_REMOTE_RX_OK … #define PORT_REMOTE_1000BT_FD … #define PORT_REMOTE_1000BT … #define PORT_REMOTE_IDLE_CNT_M … #define PORT_PHY_1000_STATIC_STATUS … #define REG_PORT_PHY_MMD_SETUP … #define PORT_MMD_OP_MODE_M … #define PORT_MMD_OP_MODE_S … #define PORT_MMD_OP_INDEX … #define PORT_MMD_OP_DATA_NO_INCR … #define PORT_MMD_OP_DATA_INCR_RW … #define PORT_MMD_OP_DATA_INCR_W … #define PORT_MMD_DEVICE_ID_M … #define MMD_SETUP(mode, dev) … #define REG_PORT_PHY_MMD_INDEX_DATA … #define MMD_DEVICE_ID_DSP … #define MMD_DSP_SQI_CHAN_A … #define MMD_DSP_SQI_CHAN_B … #define MMD_DSP_SQI_CHAN_C … #define MMD_DSP_SQI_CHAN_D … #define DSP_SQI_ERR_DETECTED … #define DSP_SQI_AVG_ERR … #define MMD_DEVICE_ID_COMMON … #define MMD_DEVICE_ID_EEE_ADV … #define MMD_EEE_ADV … #define EEE_ADV_100MBIT … #define EEE_ADV_1GBIT … #define MMD_EEE_LP_ADV … #define MMD_EEE_MSG_CODE … #define MMD_DEVICE_ID_AFED … #define REG_PORT_PHY_EXTENDED_STATUS … #define PORT_100BTX_FD_ABLE … #define PORT_100BTX_ABLE … #define PORT_10BT_FD_ABLE … #define PORT_10BT_ABLE … #define REG_PORT_SGMII_ADDR__4 … #define PORT_SGMII_AUTO_INCR … #define PORT_SGMII_DEVICE_ID_M … #define PORT_SGMII_DEVICE_ID_S … #define PORT_SGMII_ADDR_M … #define REG_PORT_SGMII_DATA__4 … #define PORT_SGMII_DATA_M … #define MMD_DEVICE_ID_PMA … #define MMD_DEVICE_ID_PCS … #define MMD_DEVICE_ID_PHY_XS … #define MMD_DEVICE_ID_DTE_XS … #define MMD_DEVICE_ID_AN … #define MMD_DEVICE_ID_VENDOR_CTRL … #define MMD_DEVICE_ID_VENDOR_MII … #define SR_MII … #define MMD_SR_MII_CTRL … #define SR_MII_RESET … #define SR_MII_LOOPBACK … #define SR_MII_SPEED_100MBIT … #define SR_MII_AUTO_NEG_ENABLE … #define SR_MII_POWER_DOWN … #define SR_MII_AUTO_NEG_RESTART … #define SR_MII_FULL_DUPLEX … #define SR_MII_SPEED_1000MBIT … #define MMD_SR_MII_STATUS … #define MMD_SR_MII_ID_1 … #define MMD_SR_MII_ID_2 … #define MMD_SR_MII_AUTO_NEGOTIATION … #define SR_MII_AUTO_NEG_NEXT_PAGE … #define SR_MII_AUTO_NEG_REMOTE_FAULT_M … #define SR_MII_AUTO_NEG_REMOTE_FAULT_S … #define SR_MII_AUTO_NEG_NO_ERROR … #define SR_MII_AUTO_NEG_OFFLINE … #define SR_MII_AUTO_NEG_LINK_FAILURE … #define SR_MII_AUTO_NEG_ERROR … #define SR_MII_AUTO_NEG_PAUSE_M … #define SR_MII_AUTO_NEG_PAUSE_S … #define SR_MII_AUTO_NEG_NO_PAUSE … #define SR_MII_AUTO_NEG_ASYM_PAUSE_TX … #define SR_MII_AUTO_NEG_SYM_PAUSE … #define SR_MII_AUTO_NEG_ASYM_PAUSE_RX … #define SR_MII_AUTO_NEG_HALF_DUPLEX … #define SR_MII_AUTO_NEG_FULL_DUPLEX … #define MMD_SR_MII_REMOTE_CAPABILITY … #define MMD_SR_MII_AUTO_NEG_EXP … #define MMD_SR_MII_AUTO_NEG_EXT … #define MMD_SR_MII_DIGITAL_CTRL_1 … #define MMD_SR_MII_AUTO_NEG_CTRL … #define SR_MII_8_BIT … #define SR_MII_SGMII_LINK_UP … #define SR_MII_TX_CFG_PHY_MASTER … #define SR_MII_PCS_MODE_M … #define SR_MII_PCS_MODE_S … #define SR_MII_PCS_SGMII … #define SR_MII_AUTO_NEG_COMPLETE_INTR … #define MMD_SR_MII_AUTO_NEG_STATUS … #define SR_MII_STAT_LINK_UP … #define SR_MII_STAT_M … #define SR_MII_STAT_S … #define SR_MII_STAT_10_MBPS … #define SR_MII_STAT_100_MBPS … #define SR_MII_STAT_1000_MBPS … #define SR_MII_STAT_FULL_DUPLEX … #define MMD_SR_MII_PHY_CTRL … #define SR_MII_PHY_LANE_SEL_M … #define SR_MII_PHY_LANE_SEL_S … #define SR_MII_PHY_WRITE … #define SR_MII_PHY_START_BUSY … #define MMD_SR_MII_PHY_ADDR … #define SR_MII_PHY_ADDR_M … #define MMD_SR_MII_PHY_DATA … #define SR_MII_PHY_DATA_M … #define SR_MII_PHY_JTAG_CHIP_ID_HI … #define SR_MII_PHY_JTAG_CHIP_ID_LO … #define REG_PORT_PHY_REMOTE_LB_LED … #define PORT_REMOTE_LOOPBACK … #define PORT_LED_SELECT … #define PORT_LED_CTRL … #define PORT_LED_CTRL_TEST … #define PORT_10BT_PREAMBLE … #define PORT_LINK_MD_10BT_ENABLE … #define PORT_LINK_MD_PASS … #define REG_PORT_PHY_LINK_MD … #define PORT_START_CABLE_DIAG … #define PORT_TX_DISABLE … #define PORT_CABLE_DIAG_PAIR_M … #define PORT_CABLE_DIAG_PAIR_S … #define PORT_CABLE_DIAG_SELECT_M … #define PORT_CABLE_DIAG_SELECT_S … #define PORT_CABLE_DIAG_RESULT_M … #define PORT_CABLE_DIAG_RESULT_S … #define PORT_CABLE_STAT_NORMAL … #define PORT_CABLE_STAT_OPEN … #define PORT_CABLE_STAT_SHORT … #define PORT_CABLE_STAT_FAILED … #define PORT_CABLE_FAULT_COUNTER … #define REG_PORT_PHY_PMA_STATUS … #define PORT_1000_LINK_GOOD … #define PORT_100_LINK_GOOD … #define REG_PORT_PHY_DIGITAL_STATUS … #define PORT_LINK_DETECT … #define PORT_SIGNAL_DETECT … #define PORT_PHY_STAT_MDI … #define PORT_PHY_STAT_MASTER … #define REG_PORT_PHY_RXER_COUNTER … #define REG_PORT_PHY_INT_ENABLE … #define REG_PORT_PHY_INT_STATUS … #define JABBER_INT … #define RX_ERR_INT … #define PAGE_RX_INT … #define PARALLEL_DETECT_FAULT_INT … #define LINK_PARTNER_ACK_INT … #define LINK_DOWN_INT … #define REMOTE_FAULT_INT … #define LINK_UP_INT … #define REG_PORT_PHY_DIGITAL_DEBUG_1 … #define PORT_REG_CLK_SPEED_25_MHZ … #define PORT_PHY_FORCE_MDI … #define PORT_PHY_AUTO_MDIX_DISABLE … /* Same as PORT_PHY_LOOPBACK */ #define PORT_PHY_PCS_LOOPBACK … #define REG_PORT_PHY_DIGITAL_DEBUG_2 … #define REG_PORT_PHY_DIGITAL_DEBUG_3 … #define PORT_100BT_FIXED_LATENCY … #define REG_PORT_PHY_PHY_CTRL … #define PORT_INT_PIN_HIGH … #define PORT_ENABLE_JABBER … #define PORT_STAT_SPEED_1000MBIT … #define PORT_STAT_SPEED_100MBIT … #define PORT_STAT_SPEED_10MBIT … #define PORT_STAT_FULL_DUPLEX … /* Same as PORT_PHY_STAT_MASTER */ #define PORT_STAT_MASTER … #define PORT_RESET … #define PORT_LINK_STATUS_FAIL … /* 3 - xMII */ #define PORT_SGMII_SEL … #define PORT_GRXC_ENABLE … #define PORT_RMII_CLK_SEL … #define PORT_MII_SEL_EDGE … #define REG_PMAVBC … #define PMAVBC_MASK … #define PMAVBC_MIN … /* 4 - MAC */ #define REG_PORT_MAC_CTRL_0 … #define PORT_BROADCAST_STORM … #define PORT_JUMBO_FRAME … #define REG_PORT_MAC_CTRL_1 … #define PORT_BACK_PRESSURE … #define PORT_PASS_ALL … #define REG_PORT_MAC_CTRL_2 … #define PORT_100BT_EEE_DISABLE … #define PORT_1000BT_EEE_DISABLE … #define REG_PORT_MAC_IN_RATE_LIMIT … #define PORT_IN_PORT_BASED_S … #define PORT_RATE_PACKET_BASED_S … #define PORT_IN_FLOW_CTRL_S … #define PORT_COUNT_IFG_S … #define PORT_COUNT_PREAMBLE_S … #define PORT_IN_PORT_BASED … #define PORT_IN_PACKET_BASED … #define PORT_IN_FLOW_CTRL … #define PORT_IN_LIMIT_MODE_M … #define PORT_IN_LIMIT_MODE_S … #define PORT_IN_ALL … #define PORT_IN_UNICAST … #define PORT_IN_MULTICAST … #define PORT_IN_BROADCAST … #define PORT_COUNT_IFG … #define PORT_COUNT_PREAMBLE … #define REG_PORT_IN_RATE_0 … #define REG_PORT_IN_RATE_1 … #define REG_PORT_IN_RATE_2 … #define REG_PORT_IN_RATE_3 … #define REG_PORT_IN_RATE_4 … #define REG_PORT_IN_RATE_5 … #define REG_PORT_IN_RATE_6 … #define REG_PORT_IN_RATE_7 … #define REG_PORT_OUT_RATE_0 … #define REG_PORT_OUT_RATE_1 … #define REG_PORT_OUT_RATE_2 … #define REG_PORT_OUT_RATE_3 … #define PORT_RATE_LIMIT_M … /* 5 - MIB Counters */ #define REG_PORT_MIB_CTRL_STAT__4 … #define MIB_COUNTER_READ … #define MIB_COUNTER_FLUSH_FREEZE … #define MIB_COUNTER_INDEX_M … #define MIB_COUNTER_INDEX_S … #define MIB_COUNTER_DATA_HI_M … #define REG_PORT_MIB_DATA … /* 6 - ACL */ #define REG_PORT_ACL_0 … #define ACL_FIRST_RULE_M … #define REG_PORT_ACL_1 … #define ACL_MODE_M … #define ACL_MODE_S … #define ACL_MODE_DISABLE … #define ACL_MODE_LAYER_2 … #define ACL_MODE_LAYER_3 … #define ACL_MODE_LAYER_4 … #define ACL_ENABLE_M … #define ACL_ENABLE_S … #define ACL_ENABLE_2_COUNT … #define ACL_ENABLE_2_TYPE … #define ACL_ENABLE_2_MAC … #define ACL_ENABLE_2_BOTH … #define ACL_ENABLE_3_IP … #define ACL_ENABLE_3_SRC_DST_COMP … #define ACL_ENABLE_4_PROTOCOL … #define ACL_ENABLE_4_TCP_PORT_COMP … #define ACL_ENABLE_4_UDP_PORT_COMP … #define ACL_ENABLE_4_TCP_SEQN_COMP … #define ACL_SRC … #define ACL_EQUAL … #define REG_PORT_ACL_2 … #define REG_PORT_ACL_3 … #define ACL_MAX_PORT … #define REG_PORT_ACL_4 … #define REG_PORT_ACL_5 … #define ACL_MIN_PORT … #define ACL_IP_ADDR … #define ACL_TCP_SEQNUM … #define REG_PORT_ACL_6 … #define ACL_RESERVED … #define ACL_PORT_MODE_M … #define ACL_PORT_MODE_S … #define ACL_PORT_MODE_DISABLE … #define ACL_PORT_MODE_EITHER … #define ACL_PORT_MODE_IN_RANGE … #define ACL_PORT_MODE_OUT_OF_RANGE … #define REG_PORT_ACL_7 … #define ACL_TCP_FLAG_ENABLE … #define REG_PORT_ACL_8 … #define ACL_TCP_FLAG_M … #define REG_PORT_ACL_9 … #define ACL_TCP_FLAG … #define ACL_ETH_TYPE … #define ACL_IP_M … #define REG_PORT_ACL_A … #define ACL_PRIO_MODE_M … #define ACL_PRIO_MODE_S … #define ACL_PRIO_MODE_DISABLE … #define ACL_PRIO_MODE_HIGHER … #define ACL_PRIO_MODE_LOWER … #define ACL_PRIO_MODE_REPLACE … #define ACL_PRIO_M … #define ACL_PRIO_S … #define ACL_VLAN_PRIO_REPLACE … #define ACL_VLAN_PRIO_M … #define ACL_VLAN_PRIO_HI_M … #define REG_PORT_ACL_B … #define ACL_VLAN_PRIO_LO_M … #define ACL_VLAN_PRIO_S … #define ACL_MAP_MODE_M … #define ACL_MAP_MODE_S … #define ACL_MAP_MODE_DISABLE … #define ACL_MAP_MODE_OR … #define ACL_MAP_MODE_AND … #define ACL_MAP_MODE_REPLACE … #define ACL_CNT_M … #define ACL_CNT_S … #define REG_PORT_ACL_C … #define REG_PORT_ACL_D … #define ACL_MSEC_UNIT … #define ACL_INTR_MODE … #define ACL_PORT_MAP … #define REG_PORT_ACL_E … #define REG_PORT_ACL_F … #define REG_PORT_ACL_BYTE_EN_MSB … #define REG_PORT_ACL_BYTE_EN_LSB … #define ACL_ACTION_START … #define ACL_ACTION_LEN … #define ACL_INTR_CNT_START … #define ACL_RULESET_START … #define ACL_RULESET_LEN … #define ACL_TABLE_LEN … #define ACL_ACTION_ENABLE … #define ACL_MATCH_ENABLE … #define ACL_RULESET_ENABLE … #define ACL_BYTE_ENABLE … #define REG_PORT_ACL_CTRL_0 … #define PORT_ACL_WRITE_DONE … #define PORT_ACL_READ_DONE … #define PORT_ACL_WRITE … #define PORT_ACL_INDEX_M … #define REG_PORT_ACL_CTRL_1 … /* 8 - Classification and Policing */ #define REG_PORT_MRI_MIRROR_CTRL … #define PORT_MIRROR_RX … #define PORT_MIRROR_TX … #define PORT_MIRROR_SNIFFER … #define REG_PORT_MRI_PRIO_CTRL … #define PORT_HIGHEST_PRIO … #define PORT_OR_PRIO … #define PORT_MAC_PRIO_ENABLE … #define PORT_VLAN_PRIO_ENABLE … #define PORT_802_1P_PRIO_ENABLE … #define PORT_DIFFSERV_PRIO_ENABLE … #define PORT_ACL_PRIO_ENABLE … #define REG_PORT_MRI_MAC_CTRL … #define PORT_USER_PRIO_CEILING … #define PORT_DROP_NON_VLAN … #define PORT_DROP_TAG … #define PORT_BASED_PRIO_M … #define PORT_BASED_PRIO_S … #define REG_PORT_MRI_AUTHEN_CTRL … #define PORT_ACL_ENABLE … #define PORT_AUTHEN_MODE … #define PORT_AUTHEN_PASS … #define PORT_AUTHEN_BLOCK … #define PORT_AUTHEN_TRAP … #define REG_PORT_MRI_INDEX__4 … #define MRI_INDEX_P_M … #define MRI_INDEX_P_S … #define MRI_INDEX_Q_M … #define MRI_INDEX_Q_S … #define REG_PORT_MRI_TC_MAP__4 … #define PORT_TC_MAP_M … #define PORT_TC_MAP_S … #define REG_PORT_MRI_POLICE_CTRL__4 … #define POLICE_DROP_ALL … #define POLICE_PACKET_TYPE_M … #define POLICE_PACKET_TYPE_S … #define POLICE_PACKET_DROPPED … #define POLICE_PACKET_GREEN … #define POLICE_PACKET_YELLOW … #define POLICE_PACKET_RED … #define PORT_BASED_POLICING … #define NON_DSCP_COLOR_M … #define NON_DSCP_COLOR_S … #define COLOR_MARK_ENABLE … #define COLOR_REMAP_ENABLE … #define POLICE_DROP_SRP … #define POLICE_COLOR_NOT_AWARE … #define POLICE_ENABLE … #define REG_PORT_POLICE_COLOR_0__4 … #define REG_PORT_POLICE_COLOR_1__4 … #define REG_PORT_POLICE_COLOR_2__4 … #define REG_PORT_POLICE_COLOR_3__4 … #define POLICE_COLOR_MAP_S … #define POLICE_COLOR_MAP_M … #define REG_PORT_POLICE_RATE__4 … #define POLICE_CIR_S … #define POLICE_PIR_S … #define REG_PORT_POLICE_BURST_SIZE__4 … #define POLICE_BURST_SIZE_M … #define POLICE_CBS_S … #define POLICE_PBS_S … #define REG_PORT_WRED_PM_CTRL_0__4 … #define WRED_PM_CTRL_M … #define WRED_PM_MAX_THRESHOLD_S … #define WRED_PM_MIN_THRESHOLD_S … #define REG_PORT_WRED_PM_CTRL_1__4 … #define WRED_PM_MULTIPLIER_S … #define WRED_PM_AVG_QUEUE_SIZE_S … #define REG_PORT_WRED_QUEUE_CTRL_0__4 … #define REG_PORT_WRED_QUEUE_CTRL_1__4 … #define REG_PORT_WRED_QUEUE_PMON__4 … #define WRED_RANDOM_DROP_ENABLE … #define WRED_PMON_FLUSH … #define WRED_DROP_GYR_DISABLE … #define WRED_DROP_YR_DISABLE … #define WRED_DROP_R_DISABLE … #define WRED_DROP_ALL … #define WRED_PMON_M … /* 9 - Shaping */ #define REG_PORT_MTI_QUEUE_CTRL_0__4 … #define MTI_PVID_REPLACE … #define REG_PORT_MTI_CREDIT_INCREMENT … /* A - QM */ #define REG_PORT_QM_CTRL__4 … #define PORT_QM_DROP_PRIO_M … #define REG_PORT_VLAN_MEMBERSHIP__4 … #define REG_PORT_QM_QUEUE_INDEX__4 … #define PORT_QM_QUEUE_INDEX_S … #define PORT_QM_BURST_SIZE_S … #define PORT_QM_MIN_RESV_SPACE_M … #define REG_PORT_QM_WATER_MARK__4 … #define PORT_QM_HI_WATER_MARK_S … #define PORT_QM_LO_WATER_MARK_S … #define PORT_QM_WATER_MARK_M … #define REG_PORT_QM_TX_CNT_0__4 … #define PORT_QM_TX_CNT_USED_S … #define PORT_QM_TX_CNT_M … #define PORT_QM_TX_CNT_MAX … #define REG_PORT_QM_TX_CNT_1__4 … #define PORT_QM_TX_CNT_CALCULATED_S … #define PORT_QM_TX_CNT_AVAIL_S … /* B - LUE */ #define REG_PORT_LUE_CTRL … #define PORT_VLAN_LOOKUP_VID_0 … #define PORT_INGRESS_FILTER … #define PORT_DISCARD_NON_VID … #define PORT_MAC_BASED_802_1X … #define PORT_SRC_ADDR_FILTER … #define REG_PORT_LUE_MSTP_INDEX … #define REG_PORT_LUE_MSTP_STATE … /* C - PTP */ #define REG_PTP_PORT_RX_DELAY__2 … #define REG_PTP_PORT_TX_DELAY__2 … #define REG_PTP_PORT_ASYM_DELAY__2 … #define REG_PTP_PORT_XDELAY_TS … #define REG_PTP_PORT_XDELAY_TS_H … #define REG_PTP_PORT_XDELAY_TS_L … #define REG_PTP_PORT_SYNC_TS … #define REG_PTP_PORT_SYNC_TS_H … #define REG_PTP_PORT_SYNC_TS_L … #define REG_PTP_PORT_PDRESP_TS … #define REG_PTP_PORT_PDRESP_TS_H … #define REG_PTP_PORT_PDRESP_TS_L … #define REG_PTP_PORT_TX_INT_STATUS__2 … #define REG_PTP_PORT_TX_INT_ENABLE__2 … #define PTP_PORT_SYNC_INT … #define PTP_PORT_XDELAY_REQ_INT … #define PTP_PORT_PDELAY_RESP_INT … #define REG_PTP_PORT_LINK_DELAY__4 … #define PRIO_QUEUES … #define RX_PRIO_QUEUES … #define KS_PRIO_IN_REG … #define TOTAL_PORT_NUM … #define KSZ9477_COUNTER_NUM … #define TOTAL_KSZ9477_COUNTER_NUM … #define SWITCH_COUNTER_NUM … #define TOTAL_SWITCH_COUNTER_NUM … #define P_BCAST_STORM_CTRL … #define P_PRIO_CTRL … #define P_MIRROR_CTRL … #define P_PHY_CTRL … #define P_RATE_LIMIT_CTRL … #define S_LINK_AGING_CTRL … #define S_MIRROR_CTRL … #define S_REPLACE_VID_CTRL … #define S_802_1P_PRIO_CTRL … #define S_TOS_PRIO_CTRL … #define S_FLUSH_TABLE_CTRL … #define SW_FLUSH_DYN_MAC_TABLE … #define MAX_TIMESTAMP_UNIT … #define MAX_TRIG_UNIT … #define MAX_TIMESTAMP_EVENT_UNIT … #define MAX_GPIO … #define PTP_TRIG_UNIT_M … #define PTP_TS_UNIT_M … #endif /* KSZ9477_REGS_H */
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