/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Microchip KSZ8795 register definitions * * Copyright (c) 2017 Microchip Technology Inc. * Tristram Ha <[email protected]> */ #ifndef __KSZ8795_REG_H #define __KSZ8795_REG_H #define KS_PORT_M … #define KS_PRIO_M … #define KS_PRIO_S … #define SW_REVISION_M … #define SW_REVISION_S … #define KSZ8863_REG_SW_RESET … #define KSZ8863_GLOBAL_SOFTWARE_RESET … #define KSZ8863_PCS_RESET … #define KSZ88X3_REG_FVID_AND_HOST_MODE … #define KSZ88X3_PORT3_RMII_CLK_INTERNAL … #define REG_SW_CTRL_0 … #define SW_NEW_BACKOFF … #define SW_GLOBAL_RESET … #define SW_FLUSH_DYN_MAC_TABLE … #define SW_FLUSH_STA_MAC_TABLE … #define SW_LINK_AUTO_AGING … #define REG_SW_CTRL_1 … #define SW_HUGE_PACKET … #define SW_TX_FLOW_CTRL_DISABLE … #define SW_RX_FLOW_CTRL_DISABLE … #define SW_CHECK_LENGTH … #define SW_AGING_ENABLE … #define SW_FAST_AGING … #define SW_AGGR_BACKOFF … #define REG_SW_CTRL_2 … #define UNICAST_VLAN_BOUNDARY … #define SW_BACK_PRESSURE … #define FAIR_FLOW_CTRL … #define NO_EXC_COLLISION_DROP … #define SW_LEGAL_PACKET_DISABLE … #define KSZ8863_HUGE_PACKET_ENABLE … #define KSZ8863_LEGAL_PACKET_ENABLE … #define REG_SW_CTRL_3 … #define WEIGHTED_FAIR_QUEUE_ENABLE … #define SW_VLAN_ENABLE … #define SW_IGMP_SNOOP … #define SW_MIRROR_RX_TX … #define REG_SW_CTRL_4 … #define SW_HALF_DUPLEX_FLOW_CTRL … #define SW_HALF_DUPLEX … #define SW_FLOW_CTRL … #define SW_10_MBIT … #define SW_REPLACE_VID … #define REG_SW_CTRL_5 … #define REG_SW_CTRL_6 … #define SW_MIB_COUNTER_FLUSH … #define SW_MIB_COUNTER_FREEZE … #define SW_MIB_COUNTER_CTRL_ENABLE … #define REG_SW_CTRL_9 … #define SPI_CLK_125_MHZ … #define SPI_CLK_62_5_MHZ … #define SPI_CLK_31_25_MHZ … #define SW_LED_MODE_M … #define SW_LED_MODE_S … #define SW_LED_LINK_ACT_SPEED … #define SW_LED_LINK_ACT … #define SW_LED_LINK_ACT_DUPLEX … #define SW_LED_LINK_DUPLEX … #define REG_SW_CTRL_10 … #define SW_PASS_PAUSE … #define REG_SW_CTRL_11 … #define REG_POWER_MANAGEMENT_1 … #define SW_PLL_POWER_DOWN … #define SW_POWER_MANAGEMENT_MODE_M … #define SW_POWER_MANAGEMENT_MODE_S … #define SW_POWER_NORMAL … #define SW_ENERGY_DETECTION … #define SW_SOFTWARE_POWER_DOWN … #define REG_POWER_MANAGEMENT_2 … #define REG_PORT_1_CTRL_0 … #define REG_PORT_2_CTRL_0 … #define REG_PORT_3_CTRL_0 … #define REG_PORT_4_CTRL_0 … #define REG_PORT_5_CTRL_0 … #define PORT_BROADCAST_STORM … #define PORT_DIFFSERV_ENABLE … #define PORT_802_1P_ENABLE … #define PORT_BASED_PRIO_S … #define PORT_BASED_PRIO_M … #define PORT_BASED_PRIO_0 … #define PORT_BASED_PRIO_1 … #define PORT_BASED_PRIO_2 … #define PORT_BASED_PRIO_3 … #define PORT_INSERT_TAG … #define PORT_REMOVE_TAG … #define KSZ8795_PORT_2QUEUE_SPLIT_EN … #define KSZ8873_PORT_4QUEUE_SPLIT_EN … #define REG_PORT_1_CTRL_1 … #define REG_PORT_2_CTRL_1 … #define REG_PORT_3_CTRL_1 … #define REG_PORT_4_CTRL_1 … #define REG_PORT_5_CTRL_1 … #define PORT_MIRROR_SNIFFER … #define PORT_MIRROR_RX … #define PORT_MIRROR_TX … #define PORT_VLAN_MEMBERSHIP … #define REG_PORT_1_CTRL_2 … #define REG_PORT_2_CTRL_2 … #define REG_PORT_3_CTRL_2 … #define REG_PORT_4_CTRL_2 … #define REG_PORT_5_CTRL_2 … #define KSZ8873_PORT_2QUEUE_SPLIT_EN … #define PORT_INGRESS_FILTER … #define PORT_DISCARD_NON_VID … #define PORT_FORCE_FLOW_CTRL … #define PORT_BACK_PRESSURE … #define REG_PORT_1_CTRL_3 … #define REG_PORT_2_CTRL_3 … #define REG_PORT_3_CTRL_3 … #define REG_PORT_4_CTRL_3 … #define REG_PORT_5_CTRL_3 … #define REG_PORT_1_CTRL_4 … #define REG_PORT_2_CTRL_4 … #define REG_PORT_3_CTRL_4 … #define REG_PORT_4_CTRL_4 … #define REG_PORT_5_CTRL_4 … #define PORT_DEFAULT_VID … #define REG_PORT_1_CTRL_5 … #define REG_PORT_2_CTRL_5 … #define REG_PORT_3_CTRL_5 … #define REG_PORT_4_CTRL_5 … #define REG_PORT_5_CTRL_5 … #define PORT_ACL_ENABLE … #define PORT_AUTHEN_MODE … #define PORT_AUTHEN_PASS … #define PORT_AUTHEN_BLOCK … #define PORT_AUTHEN_TRAP … #define REG_PORT_5_CTRL_6 … #define PORT_MII_INTERNAL_CLOCK … #define PORT_GMII_MAC_MODE … #define REG_PORT_1_CTRL_7 … #define REG_PORT_2_CTRL_7 … #define REG_PORT_3_CTRL_7 … #define REG_PORT_4_CTRL_7 … #define PORT_AUTO_NEG_ASYM_PAUSE … #define PORT_AUTO_NEG_SYM_PAUSE … #define PORT_AUTO_NEG_100BTX_FD … #define PORT_AUTO_NEG_100BTX … #define PORT_AUTO_NEG_10BT_FD … #define PORT_AUTO_NEG_10BT … #define REG_PORT_1_STATUS_0 … #define REG_PORT_2_STATUS_0 … #define REG_PORT_3_STATUS_0 … #define REG_PORT_4_STATUS_0 … /* For KSZ8765. */ #define PORT_REMOTE_ASYM_PAUSE … #define PORT_REMOTE_SYM_PAUSE … #define PORT_REMOTE_100BTX_FD … #define PORT_REMOTE_100BTX … #define PORT_REMOTE_10BT_FD … #define PORT_REMOTE_10BT … #define REG_PORT_1_STATUS_1 … #define REG_PORT_2_STATUS_1 … #define REG_PORT_3_STATUS_1 … #define REG_PORT_4_STATUS_1 … #define PORT_HP_MDIX … #define PORT_REVERSED_POLARITY … #define PORT_TX_FLOW_CTRL … #define PORT_RX_FLOW_CTRL … #define PORT_STAT_SPEED_100MBIT … #define PORT_STAT_FULL_DUPLEX … #define PORT_REMOTE_FAULT … #define REG_PORT_1_LINK_MD_CTRL … #define REG_PORT_2_LINK_MD_CTRL … #define REG_PORT_3_LINK_MD_CTRL … #define REG_PORT_4_LINK_MD_CTRL … #define PORT_CABLE_10M_SHORT … #define PORT_CABLE_DIAG_RESULT_M … #define PORT_CABLE_DIAG_RESULT_S … #define PORT_CABLE_STAT_NORMAL … #define PORT_CABLE_STAT_OPEN … #define PORT_CABLE_STAT_SHORT … #define PORT_CABLE_STAT_FAILED … #define PORT_START_CABLE_DIAG … #define PORT_FORCE_LINK … #define PORT_POWER_SAVING … #define PORT_PHY_REMOTE_LOOPBACK … #define PORT_CABLE_FAULT_COUNTER_H … #define REG_PORT_1_LINK_MD_RESULT … #define REG_PORT_2_LINK_MD_RESULT … #define REG_PORT_3_LINK_MD_RESULT … #define REG_PORT_4_LINK_MD_RESULT … #define PORT_CABLE_FAULT_COUNTER_L … #define PORT_CABLE_FAULT_COUNTER … #define REG_PORT_1_CTRL_9 … #define REG_PORT_2_CTRL_9 … #define REG_PORT_3_CTRL_9 … #define REG_PORT_4_CTRL_9 … #define PORT_AUTO_NEG_ENABLE … #define PORT_AUTO_NEG_DISABLE … #define PORT_FORCE_100_MBIT … #define PORT_FORCE_FULL_DUPLEX … #define REG_PORT_1_CTRL_10 … #define REG_PORT_2_CTRL_10 … #define REG_PORT_3_CTRL_10 … #define REG_PORT_4_CTRL_10 … #define PORT_LED_OFF … #define PORT_TX_DISABLE … #define PORT_AUTO_NEG_RESTART … #define PORT_POWER_DOWN … #define PORT_AUTO_MDIX_DISABLE … #define PORT_FORCE_MDIX … #define PORT_MAC_LOOPBACK … #define KSZ8873_PORT_PHY_LOOPBACK … #define REG_PORT_1_STATUS_2 … #define REG_PORT_2_STATUS_2 … #define REG_PORT_3_STATUS_2 … #define REG_PORT_4_STATUS_2 … #define PORT_MDIX_STATUS … #define PORT_AUTO_NEG_COMPLETE … #define PORT_STAT_LINK_GOOD … #define REG_PORT_1_STATUS_3 … #define REG_PORT_2_STATUS_3 … #define REG_PORT_3_STATUS_3 … #define REG_PORT_4_STATUS_3 … #define PORT_PHY_LOOPBACK … #define PORT_PHY_ISOLATE … #define PORT_PHY_SOFT_RESET … #define PORT_PHY_FORCE_LINK … #define PORT_PHY_MODE_M … #define PHY_MODE_IN_AUTO_NEG … #define PHY_MODE_10BT_HALF … #define PHY_MODE_100BT_HALF … #define PHY_MODE_10BT_FULL … #define PHY_MODE_100BT_FULL … #define PHY_MODE_ISOLDATE … #define REG_PORT_CTRL_0 … #define REG_PORT_CTRL_1 … #define REG_PORT_CTRL_2 … #define REG_PORT_CTRL_VID … #define REG_PORT_CTRL_5 … #define REG_PORT_STATUS_1 … #define REG_PORT_LINK_MD_CTRL … #define REG_PORT_LINK_MD_RESULT … #define REG_PORT_CTRL_9 … #define REG_PORT_CTRL_10 … #define REG_PORT_STATUS_3 … #define REG_PORT_CTRL_12 … #define REG_PORT_CTRL_13 … #define REG_PORT_RATE_CTRL_3 … #define REG_PORT_RATE_CTRL_2 … #define REG_PORT_RATE_CTRL_1 … #define REG_PORT_RATE_CTRL_0 … #define REG_PORT_RATE_LIMIT … #define REG_PORT_IN_RATE_0 … #define REG_PORT_IN_RATE_1 … #define REG_PORT_IN_RATE_2 … #define REG_PORT_IN_RATE_3 … #define REG_PORT_OUT_RATE_0 … #define REG_PORT_OUT_RATE_1 … #define REG_PORT_OUT_RATE_2 … #define REG_PORT_OUT_RATE_3 … #define PORT_CTRL_ADDR(port, addr) … #define TABLE_EXT_SELECT_S … #define TABLE_EEE_V … #define TABLE_ACL_V … #define TABLE_PME_V … #define TABLE_LINK_MD_V … #define TABLE_EEE … #define TABLE_ACL … #define TABLE_PME … #define TABLE_LINK_MD … #define TABLE_READ … #define TABLE_SELECT_S … #define TABLE_STATIC_MAC_V … #define TABLE_VLAN_V … #define TABLE_DYNAMIC_MAC_V … #define TABLE_MIB_V … #define TABLE_STATIC_MAC … #define TABLE_VLAN … #define TABLE_DYNAMIC_MAC … #define TABLE_MIB … #define REG_IND_CTRL_1 … #define TABLE_ENTRY_MASK … #define TABLE_EXT_ENTRY_MASK … #define REG_IND_DATA_5 … #define REG_IND_DATA_2 … #define REG_IND_DATA_1 … #define REG_IND_DATA_0 … #define REG_IND_DATA_PME_EEE_ACL … #define REG_INT_STATUS … #define REG_INT_ENABLE … #define INT_PME … #define REG_ACL_INT_STATUS … #define REG_ACL_INT_ENABLE … #define INT_PORT_5 … #define INT_PORT_4 … #define INT_PORT_3 … #define INT_PORT_2 … #define INT_PORT_1 … #define INT_PORT_ALL … #define REG_SW_CTRL_12 … #define REG_SW_CTRL_13 … #define SWITCH_802_1P_MASK … #define SWITCH_802_1P_BASE … #define SWITCH_802_1P_SHIFT … #define SW_802_1P_MAP_M … #define SW_802_1P_MAP_S … #define REG_SWITCH_CTRL_14 … #define SW_PRIO_MAPPING_M … #define SW_PRIO_MAPPING_S … #define SW_PRIO_MAP_3_HI … #define SW_PRIO_MAP_2_HI … #define SW_PRIO_MAP_0_LO … #define REG_SW_CTRL_15 … #define REG_SW_CTRL_16 … #define REG_SW_CTRL_17 … #define REG_SW_CTRL_18 … #define SW_SELF_ADDR_FILTER_ENABLE … #define REG_SW_UNK_UCAST_CTRL … #define REG_SW_UNK_MCAST_CTRL … #define REG_SW_UNK_VID_CTRL … #define REG_SW_UNK_IP_MCAST_CTRL … #define SW_UNK_FWD_ENABLE … #define SW_UNK_FWD_MAP … #define REG_SW_CTRL_19 … #define SW_IN_RATE_LIMIT_PERIOD_M … #define SW_IN_RATE_LIMIT_PERIOD_S … #define SW_IN_RATE_LIMIT_16_MS … #define SW_IN_RATE_LIMIT_64_MS … #define SW_IN_RATE_LIMIT_256_MS … #define SW_OUT_RATE_LIMIT_QUEUE_BASED … #define SW_INS_TAG_ENABLE … #define REG_TOS_PRIO_CTRL_0 … #define REG_TOS_PRIO_CTRL_1 … #define REG_TOS_PRIO_CTRL_2 … #define REG_TOS_PRIO_CTRL_3 … #define REG_TOS_PRIO_CTRL_4 … #define REG_TOS_PRIO_CTRL_5 … #define REG_TOS_PRIO_CTRL_6 … #define REG_TOS_PRIO_CTRL_7 … #define REG_TOS_PRIO_CTRL_8 … #define REG_TOS_PRIO_CTRL_9 … #define REG_TOS_PRIO_CTRL_10 … #define REG_TOS_PRIO_CTRL_11 … #define REG_TOS_PRIO_CTRL_12 … #define REG_TOS_PRIO_CTRL_13 … #define REG_TOS_PRIO_CTRL_14 … #define REG_TOS_PRIO_CTRL_15 … #define TOS_PRIO_M … #define TOS_PRIO_S … #define REG_SW_CTRL_21 … #define SW_IPV6_MLD_OPTION … #define SW_IPV6_MLD_SNOOP … #define REG_PORT_1_CTRL_12 … #define REG_PORT_2_CTRL_12 … #define REG_PORT_3_CTRL_12 … #define REG_PORT_4_CTRL_12 … #define REG_PORT_5_CTRL_12 … #define PORT_PASS_ALL … #define PORT_INS_TAG_FOR_PORT_5_S … #define PORT_INS_TAG_FOR_PORT_5 … #define PORT_INS_TAG_FOR_PORT_4 … #define PORT_INS_TAG_FOR_PORT_3 … #define PORT_INS_TAG_FOR_PORT_2 … #define REG_PORT_1_CTRL_13 … #define REG_PORT_2_CTRL_13 … #define REG_PORT_3_CTRL_13 … #define REG_PORT_4_CTRL_13 … #define REG_PORT_5_CTRL_13 … #define KSZ8795_PORT_4QUEUE_SPLIT_EN … #define PORT_DROP_TAG … #define REG_PORT_1_CTRL_14 … #define REG_PORT_2_CTRL_14 … #define REG_PORT_3_CTRL_14 … #define REG_PORT_4_CTRL_14 … #define REG_PORT_5_CTRL_14 … #define REG_PORT_1_CTRL_15 … #define REG_PORT_2_CTRL_15 … #define REG_PORT_3_CTRL_15 … #define REG_PORT_4_CTRL_15 … #define REG_PORT_5_CTRL_15 … #define REG_PORT_1_CTRL_16 … #define REG_PORT_2_CTRL_16 … #define REG_PORT_3_CTRL_16 … #define REG_PORT_4_CTRL_16 … #define REG_PORT_5_CTRL_16 … #define REG_PORT_1_CTRL_17 … #define REG_PORT_2_CTRL_17 … #define REG_PORT_3_CTRL_17 … #define REG_PORT_4_CTRL_17 … #define REG_PORT_5_CTRL_17 … #define REG_PORT_1_RATE_CTRL_3 … #define REG_PORT_1_RATE_CTRL_2 … #define REG_PORT_1_RATE_CTRL_1 … #define REG_PORT_1_RATE_CTRL_0 … #define REG_PORT_2_RATE_CTRL_3 … #define REG_PORT_2_RATE_CTRL_2 … #define REG_PORT_2_RATE_CTRL_1 … #define REG_PORT_2_RATE_CTRL_0 … #define REG_PORT_3_RATE_CTRL_3 … #define REG_PORT_3_RATE_CTRL_2 … #define REG_PORT_3_RATE_CTRL_1 … #define REG_PORT_3_RATE_CTRL_0 … #define REG_PORT_4_RATE_CTRL_3 … #define REG_PORT_4_RATE_CTRL_2 … #define REG_PORT_4_RATE_CTRL_1 … #define REG_PORT_4_RATE_CTRL_0 … #define REG_PORT_5_RATE_CTRL_3 … #define REG_PORT_5_RATE_CTRL_2 … #define REG_PORT_5_RATE_CTRL_1 … #define REG_PORT_5_RATE_CTRL_0 … #define RATE_CTRL_ENABLE … #define RATE_RATIO_M … #define PORT_OUT_RATE_ENABLE … #define REG_PORT_1_RATE_LIMIT … #define REG_PORT_2_RATE_LIMIT … #define REG_PORT_3_RATE_LIMIT … #define REG_PORT_4_RATE_LIMIT … #define REG_PORT_5_RATE_LIMIT … #define PORT_IN_PORT_BASED_S … #define PORT_RATE_PACKET_BASED_S … #define PORT_IN_FLOW_CTRL_S … #define PORT_IN_LIMIT_MODE_M … #define PORT_IN_LIMIT_MODE_S … #define PORT_COUNT_IFG_S … #define PORT_COUNT_PREAMBLE_S … #define PORT_IN_PORT_BASED … #define PORT_RATE_PACKET_BASED … #define PORT_IN_FLOW_CTRL … #define PORT_IN_ALL … #define PORT_IN_UNICAST … #define PORT_IN_MULTICAST … #define PORT_IN_BROADCAST … #define PORT_COUNT_IFG … #define PORT_COUNT_PREAMBLE … #define REG_PORT_1_IN_RATE_0 … #define REG_PORT_2_IN_RATE_0 … #define REG_PORT_3_IN_RATE_0 … #define REG_PORT_4_IN_RATE_0 … #define REG_PORT_5_IN_RATE_0 … #define REG_PORT_1_IN_RATE_1 … #define REG_PORT_2_IN_RATE_1 … #define REG_PORT_3_IN_RATE_1 … #define REG_PORT_4_IN_RATE_1 … #define REG_PORT_5_IN_RATE_1 … #define REG_PORT_1_IN_RATE_2 … #define REG_PORT_2_IN_RATE_2 … #define REG_PORT_3_IN_RATE_2 … #define REG_PORT_4_IN_RATE_2 … #define REG_PORT_5_IN_RATE_2 … #define REG_PORT_1_IN_RATE_3 … #define REG_PORT_2_IN_RATE_3 … #define REG_PORT_3_IN_RATE_3 … #define REG_PORT_4_IN_RATE_3 … #define REG_PORT_5_IN_RATE_3 … #define PORT_IN_RATE_ENABLE … #define PORT_RATE_LIMIT_M … #define REG_PORT_1_OUT_RATE_0 … #define REG_PORT_2_OUT_RATE_0 … #define REG_PORT_3_OUT_RATE_0 … #define REG_PORT_4_OUT_RATE_0 … #define REG_PORT_5_OUT_RATE_0 … #define REG_PORT_1_OUT_RATE_1 … #define REG_PORT_2_OUT_RATE_1 … #define REG_PORT_3_OUT_RATE_1 … #define REG_PORT_4_OUT_RATE_1 … #define REG_PORT_5_OUT_RATE_1 … #define REG_PORT_1_OUT_RATE_2 … #define REG_PORT_2_OUT_RATE_2 … #define REG_PORT_3_OUT_RATE_2 … #define REG_PORT_4_OUT_RATE_2 … #define REG_PORT_5_OUT_RATE_2 … #define REG_PORT_1_OUT_RATE_3 … #define REG_PORT_2_OUT_RATE_3 … #define REG_PORT_3_OUT_RATE_3 … #define REG_PORT_4_OUT_RATE_3 … #define REG_PORT_5_OUT_RATE_3 … /* 88x3 specific */ #define REG_SW_INSERT_SRC_PVID … /* PME */ #define SW_PME_OUTPUT_ENABLE … #define SW_PME_ACTIVE_HIGH … #define PORT_MAGIC_PACKET_DETECT … #define PORT_LINK_UP_DETECT … #define PORT_ENERGY_DETECT … /* ACL */ #define ACL_FIRST_RULE_M … #define ACL_MODE_M … #define ACL_MODE_S … #define ACL_MODE_DISABLE … #define ACL_MODE_LAYER_2 … #define ACL_MODE_LAYER_3 … #define ACL_MODE_LAYER_4 … #define ACL_ENABLE_M … #define ACL_ENABLE_S … #define ACL_ENABLE_2_COUNT … #define ACL_ENABLE_2_TYPE … #define ACL_ENABLE_2_MAC … #define ACL_ENABLE_2_BOTH … #define ACL_ENABLE_3_IP … #define ACL_ENABLE_3_SRC_DST_COMP … #define ACL_ENABLE_4_PROTOCOL … #define ACL_ENABLE_4_TCP_PORT_COMP … #define ACL_ENABLE_4_UDP_PORT_COMP … #define ACL_ENABLE_4_TCP_SEQN_COMP … #define ACL_SRC … #define ACL_EQUAL … #define ACL_MAX_PORT … #define ACL_MIN_PORT … #define ACL_IP_ADDR … #define ACL_TCP_SEQNUM … #define ACL_RESERVED … #define ACL_PORT_MODE_M … #define ACL_PORT_MODE_S … #define ACL_PORT_MODE_DISABLE … #define ACL_PORT_MODE_EITHER … #define ACL_PORT_MODE_IN_RANGE … #define ACL_PORT_MODE_OUT_OF_RANGE … #define ACL_TCP_FLAG_ENABLE … #define ACL_TCP_FLAG_M … #define ACL_TCP_FLAG … #define ACL_ETH_TYPE … #define ACL_IP_M … #define ACL_PRIO_MODE_M … #define ACL_PRIO_MODE_S … #define ACL_PRIO_MODE_DISABLE … #define ACL_PRIO_MODE_HIGHER … #define ACL_PRIO_MODE_LOWER … #define ACL_PRIO_MODE_REPLACE … #define ACL_PRIO_M … #define ACL_PRIO_S … #define ACL_VLAN_PRIO_REPLACE … #define ACL_VLAN_PRIO_M … #define ACL_VLAN_PRIO_HI_M … #define ACL_VLAN_PRIO_LO_M … #define ACL_VLAN_PRIO_S … #define ACL_MAP_MODE_M … #define ACL_MAP_MODE_S … #define ACL_MAP_MODE_DISABLE … #define ACL_MAP_MODE_OR … #define ACL_MAP_MODE_AND … #define ACL_MAP_MODE_REPLACE … #define ACL_MAP_PORT_M … #define ACL_CNT_M … #define ACL_CNT_S … #define ACL_MSEC_UNIT … #define ACL_INTR_MODE … #define REG_PORT_ACL_BYTE_EN_MSB … #define ACL_BYTE_EN_MSB_M … #define REG_PORT_ACL_BYTE_EN_LSB … #define ACL_ACTION_START … #define ACL_ACTION_LEN … #define ACL_INTR_CNT_START … #define ACL_RULESET_START … #define ACL_RULESET_LEN … #define ACL_TABLE_LEN … #define ACL_ACTION_ENABLE … #define ACL_MATCH_ENABLE … #define ACL_RULESET_ENABLE … #define ACL_BYTE_ENABLE … #define ACL_MODE_ENABLE … #define REG_PORT_ACL_CTRL_0 … #define PORT_ACL_WRITE_DONE … #define PORT_ACL_READ_DONE … #define PORT_ACL_WRITE … #define PORT_ACL_INDEX_M … #define REG_PORT_ACL_CTRL_1 … #define PORT_ACL_FORCE_DLR_MISS … #define KSZ8795_ID_HI … #define KSZ8795_ID_LO … #define KSZ8863_ID_LO … #define KSZ8795_SW_ID … #define PHY_REG_LINK_MD … #define PHY_START_CABLE_DIAG … #define PHY_CABLE_DIAG_RESULT_M … #define PHY_CABLE_DIAG_RESULT … #define PHY_CABLE_STAT_NORMAL … #define PHY_CABLE_STAT_OPEN … #define PHY_CABLE_STAT_SHORT … #define PHY_CABLE_STAT_FAILED … #define PHY_CABLE_10M_SHORT … #define PHY_CABLE_FAULT_COUNTER_M … #define PHY_REG_PHY_CTRL … #define PHY_MODE_M … #define PHY_MODE_S … #define PHY_STAT_REVERSED_POLARITY … #define PHY_STAT_MDIX … #define PHY_FORCE_LINK … #define PHY_POWER_SAVING_ENABLE … #define PHY_REMOTE_LOOPBACK … /* Chip resource */ #define PRIO_QUEUES … #define KS_PRIO_IN_REG … #define MIB_COUNTER_NUM … /* Common names used by other drivers */ #define P_BCAST_STORM_CTRL … #define P_PRIO_CTRL … #define P_TAG_CTRL … #define P_MIRROR_CTRL … #define P_802_1P_CTRL … #define P_PASS_ALL_CTRL … #define P_INS_SRC_PVID_CTRL … #define P_DROP_TAG_CTRL … #define P_RATE_LIMIT_CTRL … #define S_UNKNOWN_DA_CTRL … #define S_FORWARD_INVALID_VID_CTRL … #define S_FLUSH_TABLE_CTRL … #define S_LINK_AGING_CTRL … #define S_HUGE_PACKET_CTRL … #define S_MIRROR_CTRL … #define S_REPLACE_VID_CTRL … #define S_PASS_PAUSE_CTRL … #define S_802_1P_PRIO_CTRL … #define S_TOS_PRIO_CTRL … #define S_IPV6_MLD_CTRL … #define IND_ACC_TABLE(table) … /* */ #define REG_IND_EEE_GLOB2_LO … #define REG_IND_EEE_GLOB2_HI … /** * MIB_COUNTER_VALUE 00-00000000-3FFFFFFF * MIB_TOTAL_BYTES 00-0000000F-FFFFFFFF * MIB_PACKET_DROPPED 00-00000000-0000FFFF * MIB_COUNTER_VALID 00-00000020-00000000 * MIB_COUNTER_OVERFLOW 00-00000040-00000000 */ #define MIB_COUNTER_VALUE … #define KSZ8795_MIB_TOTAL_RX_0 … #define KSZ8795_MIB_TOTAL_TX_0 … #define KSZ8795_MIB_TOTAL_RX_1 … #define KSZ8795_MIB_TOTAL_TX_1 … #define KSZ8863_MIB_PACKET_DROPPED_TX_0 … #define KSZ8863_MIB_PACKET_DROPPED_RX_0 … #define MIB_PACKET_DROPPED … #define MIB_TOTAL_BYTES_H … #define TAIL_TAG_OVERRIDE … #define TAIL_TAG_LOOKUP … #define FID_ENTRIES … #define KSZ8_DYN_MAC_ENTRIES … #endif
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