// SPDX-License-Identifier: GPL-2.0 /* * corePWM driver for Microchip "soft" FPGA IP cores. * * Copyright (c) 2021-2023 Microchip Corporation. All rights reserved. * Author: Conor Dooley <[email protected]> * Documentation: * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb * * Limitations: * - If the IP block is configured without "shadow registers", all register * writes will take effect immediately, causing glitches on the output. * If shadow registers *are* enabled, setting the "SYNC_UPDATE" register * notifies the core that it needs to update the registers defining the * waveform from the contents of the "shadow registers". Otherwise, changes * will take effective immediately, even for those channels. * As setting the period/duty cycle takes 4 register writes, there is a window * in which this races against the start of a new period. * - The IP block has no concept of a duty cycle, only rising/falling edges of * the waveform. Unfortunately, if the rising & falling edges registers have * the same value written to them the IP block will do whichever of a rising * or a falling edge is possible. I.E. a 50% waveform at twice the requested * period. Therefore to get a 0% waveform, the output is set the max high/low * time depending on polarity. * If the duty cycle is 0%, and the requested period is less than the * available period resolution, this will manifest as a ~100% waveform (with * some output glitches) rather than 50%. * - The PWM period is set for the whole IP block not per channel. The driver * will only change the period if no other PWM output is enabled. */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> #include <linux/ktime.h> #include <linux/math.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pwm.h> #define MCHPCOREPWM_PRESCALE_MAX … #define MCHPCOREPWM_PERIOD_STEPS_MAX … #define MCHPCOREPWM_PERIOD_MAX … #define MCHPCOREPWM_PRESCALE … #define MCHPCOREPWM_PERIOD … #define MCHPCOREPWM_EN(i) … #define MCHPCOREPWM_POSEDGE(i) … #define MCHPCOREPWM_NEGEDGE(i) … #define MCHPCOREPWM_SYNC_UPD … #define MCHPCOREPWM_TIMEOUT_MS … struct mchp_core_pwm_chip { … }; static inline struct mchp_core_pwm_chip *to_mchp_core_pwm(struct pwm_chip *chip) { … } static void mchp_core_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, bool enable, u64 period) { … } static void mchp_core_pwm_wait_for_sync_update(struct mchp_core_pwm_chip *mchp_core_pwm, unsigned int channel) { … } static u64 mchp_core_pwm_calc_duty(const struct pwm_state *state, u64 clk_rate, u8 prescale, u8 period_steps) { … } static void mchp_core_pwm_apply_duty(struct pwm_chip *chip, struct pwm_device *pwm, const struct pwm_state *state, u64 duty_steps, u16 period_steps) { … } static int mchp_core_pwm_calc_period(const struct pwm_state *state, unsigned long clk_rate, u16 *prescale, u16 *period_steps) { … } static int mchp_core_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm, const struct pwm_state *state) { … } static int mchp_core_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, const struct pwm_state *state) { … } static int mchp_core_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state) { … } static const struct pwm_ops mchp_core_pwm_ops = …; static const struct of_device_id mchp_core_of_match[] = …; MODULE_DEVICE_TABLE(of, mchp_core_of_match); static int mchp_core_pwm_probe(struct platform_device *pdev) { … } static struct platform_driver mchp_core_pwm_driver = …; module_platform_driver(…) …; MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
Codebase Browser
linux