/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Marvell 88E6xxx Switch Global (1) Registers support * * Copyright (c) 2008 Marvell Semiconductor * * Copyright (c) 2016-2017 Savoir-faire Linux Inc. * Vivien Didelot <[email protected]> */ #ifndef _MV88E6XXX_GLOBAL1_H #define _MV88E6XXX_GLOBAL1_H #include "chip.h" /* Offset 0x00: Switch Global Status Register */ #define MV88E6XXX_G1_STS … #define MV88E6352_G1_STS_PPU_STATE … #define MV88E6185_G1_STS_PPU_STATE_MASK … #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST … #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING … #define MV88E6185_G1_STS_PPU_STATE_DISABLED … #define MV88E6185_G1_STS_PPU_STATE_POLLING … #define MV88E6XXX_G1_STS_INIT_READY … #define MV88E6393X_G1_STS_IRQ_DEVICE_2 … #define MV88E6XXX_G1_STS_IRQ_AVB … #define MV88E6XXX_G1_STS_IRQ_DEVICE … #define MV88E6XXX_G1_STS_IRQ_STATS … #define MV88E6XXX_G1_STS_IRQ_VTU_PROB … #define MV88E6XXX_G1_STS_IRQ_VTU_DONE … #define MV88E6XXX_G1_STS_IRQ_ATU_PROB … #define MV88E6XXX_G1_STS_IRQ_ATU_DONE … #define MV88E6XXX_G1_STS_IRQ_TCAM_DONE … #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE … /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 */ #define MV88E6XXX_G1_MAC_01 … #define MV88E6XXX_G1_MAC_23 … #define MV88E6XXX_G1_MAC_45 … /* Offset 0x01: ATU FID Register */ #define MV88E6352_G1_ATU_FID … /* Offset 0x02: VTU FID Register */ #define MV88E6352_G1_VTU_FID … #define MV88E6352_G1_VTU_FID_VID_POLICY … #define MV88E6352_G1_VTU_FID_MASK … /* Offset 0x03: VTU SID Register */ #define MV88E6352_G1_VTU_SID … #define MV88E6352_G1_VTU_SID_MASK … /* Offset 0x04: Switch Global Control Register */ #define MV88E6XXX_G1_CTL1 … #define MV88E6XXX_G1_CTL1_SW_RESET … #define MV88E6XXX_G1_CTL1_PPU_ENABLE … #define MV88E6352_G1_CTL1_DISCARD_EXCESS … #define MV88E6185_G1_CTL1_SCHED_PRIO … #define MV88E6185_G1_CTL1_MAX_FRAME_1632 … #define MV88E6185_G1_CTL1_RELOAD_EEPROM … #define MV88E6393X_G1_CTL1_DEVICE2_EN … #define MV88E6XXX_G1_CTL1_DEVICE_EN … #define MV88E6XXX_G1_CTL1_STATS_DONE_EN … #define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN … #define MV88E6XXX_G1_CTL1_VTU_DONE_EN … #define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN … #define MV88E6XXX_G1_CTL1_ATU_DONE_EN … #define MV88E6XXX_G1_CTL1_TCAM_EN … #define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN … /* Offset 0x05: VTU Operation Register */ #define MV88E6XXX_G1_VTU_OP … #define MV88E6XXX_G1_VTU_OP_BUSY … #define MV88E6XXX_G1_VTU_OP_MASK … #define MV88E6XXX_G1_VTU_OP_FLUSH_ALL … #define MV88E6XXX_G1_VTU_OP_NOOP … #define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE … #define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT … #define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE … #define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT … #define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION … #define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION … #define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION … #define MV88E6XXX_G1_VTU_OP_SPID_MASK … /* Offset 0x06: VTU VID Register */ #define MV88E6XXX_G1_VTU_VID … #define MV88E6XXX_G1_VTU_VID_MASK … #define MV88E6390_G1_VTU_VID_PAGE … #define MV88E6XXX_G1_VTU_VID_VALID … /* Offset 0x07: VTU/STU Data Register 1 * Offset 0x08: VTU/STU Data Register 2 * Offset 0x09: VTU/STU Data Register 3 */ #define MV88E6XXX_G1_VTU_DATA1 … #define MV88E6XXX_G1_VTU_DATA2 … #define MV88E6XXX_G1_VTU_DATA3 … #define MV88E6XXX_G1_VTU_STU_DATA_MASK … #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED … #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED … #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED … #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER … #define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED … #define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING … #define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING … #define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING … /* Offset 0x0A: ATU Control Register */ #define MV88E6XXX_G1_ATU_CTL … #define MV88E6XXX_G1_ATU_CTL_LEARN2ALL … #define MV88E6161_G1_ATU_CTL_HASH_MASK … /* Offset 0x0B: ATU Operation Register */ #define MV88E6XXX_G1_ATU_OP … #define MV88E6XXX_G1_ATU_OP_BUSY … #define MV88E6XXX_G1_ATU_OP_MASK … #define MV88E6XXX_G1_ATU_OP_NOOP … #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL … #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC … #define MV88E6XXX_G1_ATU_OP_LOAD_DB … #define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB … #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB … #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB … #define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION … #define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION … #define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION … #define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION … #define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION … /* Offset 0x0C: ATU Data Register */ #define MV88E6XXX_G1_ATU_DATA … #define MV88E6XXX_G1_ATU_DATA_TRUNK … #define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK … #define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK … #define MV88E6XXX_G1_ATU_DATA_STATE_MASK … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2 … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3 … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4 … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5 … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6 … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC … #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO … #define MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED … #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY … #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL … #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT … #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC … #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO … #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO … #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO … #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO … /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1 * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3 * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5 */ #define MV88E6XXX_G1_ATU_MAC01 … #define MV88E6XXX_G1_ATU_MAC23 … #define MV88E6XXX_G1_ATU_MAC45 … /* Offset 0x10: IP-PRI Mapping Register 0 * Offset 0x11: IP-PRI Mapping Register 1 * Offset 0x12: IP-PRI Mapping Register 2 * Offset 0x13: IP-PRI Mapping Register 3 * Offset 0x14: IP-PRI Mapping Register 4 * Offset 0x15: IP-PRI Mapping Register 5 * Offset 0x16: IP-PRI Mapping Register 6 * Offset 0x17: IP-PRI Mapping Register 7 */ #define MV88E6XXX_G1_IP_PRI_0 … #define MV88E6XXX_G1_IP_PRI_1 … #define MV88E6XXX_G1_IP_PRI_2 … #define MV88E6XXX_G1_IP_PRI_3 … #define MV88E6XXX_G1_IP_PRI_4 … #define MV88E6XXX_G1_IP_PRI_5 … #define MV88E6XXX_G1_IP_PRI_6 … #define MV88E6XXX_G1_IP_PRI_7 … /* Offset 0x18: IEEE-PRI Register */ #define MV88E6XXX_G1_IEEE_PRI … /* Offset 0x19: Core Tag Type */ #define MV88E6185_G1_CORE_TAG_TYPE … /* Offset 0x1A: Monitor Control */ #define MV88E6185_G1_MONITOR_CTL … #define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK … #define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK … #define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK … #define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK … #define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK … /* Offset 0x1A: Monitor & MGMT Control Register */ #define MV88E6390_G1_MONITOR_MGMT_CTL … #define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE … #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK … #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO … #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI … #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO … #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI … #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST … #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST … #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST … #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_PTP_CPU_DEST … #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI … #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK … /* Offset 0x1C: Global Control 2 */ #define MV88E6XXX_G1_CTL2 … #define MV88E6185_G1_CTL2_CASCADE_PORT_MASK … #define MV88E6185_G1_CTL2_CASCADE_PORT_NONE … #define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI … #define MV88E6352_G1_CTL2_HEADER_TYPE_MASK … #define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG … #define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT … #define MV88E6390_G1_CTL2_HEADER_TYPE_LAG … #define MV88E6352_G1_CTL2_RMU_MODE_MASK … #define MV88E6352_G1_CTL2_RMU_MODE_DISABLED … #define MV88E6352_G1_CTL2_RMU_MODE_PORT_4 … #define MV88E6352_G1_CTL2_RMU_MODE_PORT_5 … #define MV88E6352_G1_CTL2_RMU_MODE_PORT_6 … #define MV88E6085_G1_CTL2_DA_CHECK … #define MV88E6085_G1_CTL2_P10RM … #define MV88E6085_G1_CTL2_RM_ENABLE … #define MV88E6352_G1_CTL2_DA_CHECK … #define MV88E6390_G1_CTL2_RMU_MODE_MASK … #define MV88E6390_G1_CTL2_RMU_MODE_PORT_0 … #define MV88E6390_G1_CTL2_RMU_MODE_PORT_1 … #define MV88E6390_G1_CTL2_RMU_MODE_PORT_9 … #define MV88E6390_G1_CTL2_RMU_MODE_PORT_10 … #define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA … #define MV88E6390_G1_CTL2_RMU_MODE_DISABLED … #define MV88E6390_G1_CTL2_HIST_MODE_MASK … #define MV88E6390_G1_CTL2_HIST_MODE_RX … #define MV88E6390_G1_CTL2_HIST_MODE_TX … #define MV88E6352_G1_CTL2_CTR_MODE_MASK … #define MV88E6390_G1_CTL2_CTR_MODE … #define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK … /* Offset 0x1D: Stats Operation Register */ #define MV88E6XXX_G1_STATS_OP … #define MV88E6XXX_G1_STATS_OP_BUSY … #define MV88E6XXX_G1_STATS_OP_NOP … #define MV88E6XXX_G1_STATS_OP_FLUSH_ALL … #define MV88E6XXX_G1_STATS_OP_FLUSH_PORT … #define MV88E6XXX_G1_STATS_OP_READ_CAPTURED … #define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT … #define MV88E6XXX_G1_STATS_OP_HIST_RX … #define MV88E6XXX_G1_STATS_OP_HIST_TX … #define MV88E6XXX_G1_STATS_OP_HIST_RX_TX … #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9 … #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10 … /* Offset 0x1E: Stats Counter Register Bytes 3 & 2 * Offset 0x1F: Stats Counter Register Bytes 1 & 0 */ #define MV88E6XXX_G1_STATS_COUNTER_32 … #define MV88E6XXX_G1_STATS_COUNTER_01 … int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val); int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int bit, int val); int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, u16 mask, u16 val); int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip); int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip); int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip); int mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip); int mv88e6250_g1_wait_eeprom_done_prereset(struct mv88e6xxx_chip *chip); int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip); int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip); int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu); int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip); int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip); void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val); int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip); int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, enum mv88e6xxx_egress_direction direction, int port); int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, enum mv88e6xxx_egress_direction direction, int port); int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port); int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port); int mv88e6390_g1_set_ptp_cpu_port(struct mv88e6xxx_chip *chip, int port); int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip); int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip); int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip); int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port); int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip); int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip); int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip); int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index); int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all); int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip, unsigned int msecs); int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, struct mv88e6xxx_atu_entry *entry); int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid, struct mv88e6xxx_atu_entry *entry); int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all); int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port, bool all); int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip); void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip); int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash); int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash); int mv88e6xxx_g1_vtu_getnext(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry); int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry); int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry); int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry); int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry); int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry); int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, struct mv88e6xxx_vtu_entry *entry); int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip); int mv88e6xxx_g1_stu_getnext(struct mv88e6xxx_chip *chip, struct mv88e6xxx_stu_entry *entry); int mv88e6352_g1_stu_getnext(struct mv88e6xxx_chip *chip, struct mv88e6xxx_stu_entry *entry); int mv88e6352_g1_stu_loadpurge(struct mv88e6xxx_chip *chip, struct mv88e6xxx_stu_entry *entry); int mv88e6390_g1_stu_getnext(struct mv88e6xxx_chip *chip, struct mv88e6xxx_stu_entry *entry); int mv88e6390_g1_stu_loadpurge(struct mv88e6xxx_chip *chip, struct mv88e6xxx_stu_entry *entry); int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip); void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip); int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid); #endif /* _MV88E6XXX_GLOBAL1_H */
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