linux/drivers/net/dsa/mv88e6xxx/global2.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Marvell 88E6xxx Switch Global 2 Registers support
 *
 * Copyright (c) 2008 Marvell Semiconductor
 *
 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
 *	Vivien Didelot <[email protected]>
 */

#include <linux/bitfield.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>

#include "chip.h"
#include "global1.h" /* for MV88E6XXX_G1_STS_IRQ_DEVICE */
#include "global2.h"

int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
{ … }

int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
{ … }

int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
			  bit, int val)
{ … }

/* Offset 0x00: Interrupt Source Register */

static int mv88e6xxx_g2_int_source(struct mv88e6xxx_chip *chip, u16 *src)
{ … }

/* Offset 0x01: Interrupt Mask Register */

static int mv88e6xxx_g2_int_mask(struct mv88e6xxx_chip *chip, u16 mask)
{ … }

/* Offset 0x02: Management Enable 2x */

static int mv88e6xxx_g2_mgmt_enable_2x(struct mv88e6xxx_chip *chip, u16 en2x)
{ … }

/* Offset 0x03: Management Enable 0x */

static int mv88e6xxx_g2_mgmt_enable_0x(struct mv88e6xxx_chip *chip, u16 en0x)
{ … }

/* Offset 0x05: Switch Management Register */

static int mv88e6xxx_g2_switch_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip,
					     bool enable)
{ … }

int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
{ … }

/* Offset 0x06: Device Mapping Table register */

int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
				      int port)
{ … }

/* Offset 0x07: Trunk Mask Table register */

int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
				  bool hash, u16 mask)
{ … }

/* Offset 0x08: Trunk Mapping Table register */

int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
				     u16 map)
{ … }

int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip)
{ … }

/* Offset 0x09: Ingress Rate Command register
 * Offset 0x0A: Ingress Rate Data register
 */

static int mv88e6xxx_g2_irl_wait(struct mv88e6xxx_chip *chip)
{ … }

static int mv88e6xxx_g2_irl_op(struct mv88e6xxx_chip *chip, u16 op, int port,
			       int res, int reg)
{ … }

int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
{ … }

int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
{ … }

/* Offset 0x0B: Cross-chip Port VLAN (Addr) Register
 * Offset 0x0C: Cross-chip Port VLAN Data Register
 */

static int mv88e6xxx_g2_pvt_op_wait(struct mv88e6xxx_chip *chip)
{ … }

static int mv88e6xxx_g2_pvt_op(struct mv88e6xxx_chip *chip, int src_dev,
			       int src_port, u16 op)
{ … }

int mv88e6xxx_g2_pvt_read(struct mv88e6xxx_chip *chip, int src_dev,
			  int src_port, u16 *data)
{ … }

int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
			   int src_port, u16 data)
{ … }

/* Offset 0x0D: Switch MAC/WoL/WoF register */

static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
					 unsigned int pointer, u8 data)
{ … }

int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
{ … }

/* Offset 0x0E: ATU Statistics */

int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin)
{ … }

int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats)
{ … }

/* Offset 0x0F: Priority Override Table */

static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
				  u8 data)
{ … }

int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip)
{ … }

/* Offset 0x14: EEPROM Command
 * Offset 0x15: EEPROM Data (for 16-bit data access)
 * Offset 0x15: EEPROM Addr (for 8-bit data access)
 */

int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
{ … }

static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
{ … }

static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip,
				     u16 addr, u8 *data)
{ … }

static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip,
				      u16 addr, u8 data)
{ … }

static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
				      u8 addr, u16 *data)
{ … }

static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
				       u8 addr, u16 data)
{ … }

int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
			     struct ethtool_eeprom *eeprom, u8 *data)
{ … }

int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
			     struct ethtool_eeprom *eeprom, u8 *data)
{ … }

int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
			      struct ethtool_eeprom *eeprom, u8 *data)
{ … }

int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
			      struct ethtool_eeprom *eeprom, u8 *data)
{ … }

/* Offset 0x18: SMI PHY Command Register
 * Offset 0x19: SMI PHY Data Register
 */

static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
{ … }

static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
{ … }

static int mv88e6xxx_g2_smi_phy_access(struct mv88e6xxx_chip *chip,
				       bool external, bool c45, u16 op, int dev,
				       int reg)
{ … }

static int mv88e6xxx_g2_smi_phy_access_c22(struct mv88e6xxx_chip *chip,
					   bool external, u16 op, int dev,
					   int reg)
{ … }

/* IEEE 802.3 Clause 22 Read Data Register */
static int mv88e6xxx_g2_smi_phy_read_data_c22(struct mv88e6xxx_chip *chip,
					      bool external, int dev, int reg,
					      u16 *data)
{ … }

/* IEEE 802.3 Clause 22 Write Data Register */
static int mv88e6xxx_g2_smi_phy_write_data_c22(struct mv88e6xxx_chip *chip,
					       bool external, int dev, int reg,
					       u16 data)
{ … }

static int mv88e6xxx_g2_smi_phy_access_c45(struct mv88e6xxx_chip *chip,
					   bool external, u16 op, int port,
					   int dev)
{ … }

/* IEEE 802.3 Clause 45 Write Address Register */
static int mv88e6xxx_g2_smi_phy_write_addr_c45(struct mv88e6xxx_chip *chip,
					       bool external, int port, int dev,
					       int addr)
{ … }

/* IEEE 802.3 Clause 45 Read Data Register */
static int mv88e6xxx_g2_smi_phy_read_data_c45(struct mv88e6xxx_chip *chip,
					      bool external, int port, int dev,
					      u16 *data)
{ … }

static int _mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
					  bool external, int port, int devad,
					  int reg, u16 *data)
{ … }

/* IEEE 802.3 Clause 45 Write Data Register */
static int mv88e6xxx_g2_smi_phy_write_data_c45(struct mv88e6xxx_chip *chip,
					       bool external, int port, int dev,
					       u16 data)
{ … }

static int _mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
					   bool external, int port, int devad,
					   int reg, u16 data)
{ … }

int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip,
				  struct mii_bus *bus,
				  int addr, int reg, u16 *val)
{ … }

int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
				  struct mii_bus *bus, int addr, int devad,
				  int reg, u16 *val)
{ … }

int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip,
				   struct mii_bus *bus, int addr, int reg,
				   u16 val)
{ … }

int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
				   struct mii_bus *bus, int addr, int devad,
				   int reg, u16 val)
{ … }

/* Offset 0x1B: Watchdog Control */
static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
{ … }

static void mv88e6097_watchdog_free(struct mv88e6xxx_chip *chip)
{ … }

static int mv88e6097_watchdog_setup(struct mv88e6xxx_chip *chip)
{ … }

const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = …;

static void mv88e6250_watchdog_free(struct mv88e6xxx_chip *chip)
{ … }

static int mv88e6250_watchdog_setup(struct mv88e6xxx_chip *chip)
{ … }

const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops = …;

static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip)
{ … }

static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
{ … }

static void mv88e6390_watchdog_free(struct mv88e6xxx_chip *chip)
{ … }

const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = …;

static int mv88e6393x_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
{ … }

const struct mv88e6xxx_irq_ops mv88e6393x_watchdog_ops = …;

static irqreturn_t mv88e6xxx_g2_watchdog_thread_fn(int irq, void *dev_id)
{ … }

static void mv88e6xxx_g2_watchdog_free(struct mv88e6xxx_chip *chip)
{ … }

static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip)
{ … }

/* Offset 0x1D: Misc Register */

static int mv88e6xxx_g2_misc_5_bit_port(struct mv88e6xxx_chip *chip,
					bool port_5_bit)
{ … }

int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
{ … }

static void mv88e6xxx_g2_irq_mask(struct irq_data *d)
{ … }

static void mv88e6xxx_g2_irq_unmask(struct irq_data *d)
{ … }

static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id)
{ … }

static void mv88e6xxx_g2_irq_bus_lock(struct irq_data *d)
{ … }

static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d)
{ … }

static const struct irq_chip mv88e6xxx_g2_irq_chip = …;

static int mv88e6xxx_g2_irq_domain_map(struct irq_domain *d,
				       unsigned int irq,
				       irq_hw_number_t hwirq)
{ … }

static const struct irq_domain_ops mv88e6xxx_g2_irq_domain_ops = …;

void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
				struct mii_bus *bus)
{ … }

void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
				struct mii_bus *bus)
{ … }