/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Marvell 88E6xxx SERDES manipulation, via SMI bus * * Copyright (c) 2008 Marvell Semiconductor * * Copyright (c) 2016 Andrew Lunn <[email protected]> */ #ifndef _MV88E6XXX_SERDES_H #define _MV88E6XXX_SERDES_H #include "chip.h" struct phylink_link_state; #define MV88E6352_ADDR_SERDES … #define MV88E6352_SERDES_PAGE_FIBER … #define MV88E6352_SERDES_IRQ … #define MV88E6352_SERDES_INT_ENABLE … #define MV88E6352_SERDES_INT_SPEED_CHANGE … #define MV88E6352_SERDES_INT_DUPLEX_CHANGE … #define MV88E6352_SERDES_INT_PAGE_RX … #define MV88E6352_SERDES_INT_AN_COMPLETE … #define MV88E6352_SERDES_INT_LINK_CHANGE … #define MV88E6352_SERDES_INT_SYMBOL_ERROR … #define MV88E6352_SERDES_INT_FALSE_CARRIER … #define MV88E6352_SERDES_INT_FIFO_OVER_UNDER … #define MV88E6352_SERDES_INT_FIBRE_ENERGY … #define MV88E6352_SERDES_INT_STATUS … #define MV88E6352_SERDES_SPEC_CTRL2 … #define MV88E6352_SERDES_OUT_AMP_MASK … #define MV88E6341_PORT5_LANE … #define MV88E6390_PORT9_LANE0 … #define MV88E6390_PORT9_LANE1 … #define MV88E6390_PORT9_LANE2 … #define MV88E6390_PORT9_LANE3 … #define MV88E6390_PORT10_LANE0 … #define MV88E6390_PORT10_LANE1 … #define MV88E6390_PORT10_LANE2 … #define MV88E6390_PORT10_LANE3 … /* 10GBASE-R and 10GBASE-X4/X2 */ #define MV88E6390_10G_CTRL1 … #define MV88E6390_10G_STAT1 … #define MV88E6390_10G_INT_ENABLE … #define MV88E6390_10G_INT_LINK_DOWN … #define MV88E6390_10G_INT_LINK_UP … #define MV88E6390_10G_INT_STATUS … #define MV88E6393X_10G_INT_ENABLE … #define MV88E6393X_10G_INT_LINK_CHANGE … #define MV88E6393X_10G_INT_STATUS … /* USXGMII */ #define MV88E6390_USXGMII_LP_STATUS … #define MV88E6390_USXGMII_PHY_STATUS … /* 1000BASE-X and SGMII */ #define MV88E6390_SGMII_BMCR … #define MV88E6390_SGMII_BMSR … #define MV88E6390_SGMII_ADVERTISE … #define MV88E6390_SGMII_LPA … #define MV88E6390_SGMII_INT_ENABLE … #define MV88E6390_SGMII_INT_SPEED_CHANGE … #define MV88E6390_SGMII_INT_DUPLEX_CHANGE … #define MV88E6390_SGMII_INT_PAGE_RX … #define MV88E6390_SGMII_INT_AN_COMPLETE … #define MV88E6390_SGMII_INT_LINK_DOWN … #define MV88E6390_SGMII_INT_LINK_UP … #define MV88E6390_SGMII_INT_SYMBOL_ERROR … #define MV88E6390_SGMII_INT_FALSE_CARRIER … #define MV88E6390_SGMII_INT_STATUS … #define MV88E6390_SGMII_PHY_STATUS … #define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK … #define MV88E6390_SGMII_PHY_STATUS_SPEED_1000 … #define MV88E6390_SGMII_PHY_STATUS_SPEED_100 … #define MV88E6390_SGMII_PHY_STATUS_SPEED_10 … #define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL … #define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID … #define MV88E6390_SGMII_PHY_STATUS_LINK … #define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE … #define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE … /* Packet generator pad packet checker */ #define MV88E6390_PG_CONTROL … #define MV88E6390_PG_CONTROL_ENABLE_PC … #define MV88E6393X_PORT0_LANE … #define MV88E6393X_PORT9_LANE … #define MV88E6393X_PORT10_LANE … /* Port Operational Configuration */ #define MV88E6393X_SERDES_POC … #define MV88E6393X_SERDES_POC_PCS_1000BASEX … #define MV88E6393X_SERDES_POC_PCS_2500BASEX … #define MV88E6393X_SERDES_POC_PCS_SGMII_PHY … #define MV88E6393X_SERDES_POC_PCS_SGMII_MAC … #define MV88E6393X_SERDES_POC_PCS_5GBASER … #define MV88E6393X_SERDES_POC_PCS_10GBASER … #define MV88E6393X_SERDES_POC_PCS_USXGMII_PHY … #define MV88E6393X_SERDES_POC_PCS_USXGMII_MAC … #define MV88E6393X_SERDES_POC_PCS_MASK … #define MV88E6393X_SERDES_POC_RESET … #define MV88E6393X_SERDES_POC_PDOWN … #define MV88E6393X_SERDES_POC_AN … #define MV88E6393X_SERDES_CTRL1 … #define MV88E6393X_SERDES_CTRL1_TX_PDOWN … #define MV88E6393X_SERDES_CTRL1_RX_PDOWN … #define MV88E6393X_ERRATA_4_8_REG … #define MV88E6393X_ERRATA_4_8_BIT … int mv88e6xxx_pcs_decode_state(struct device *dev, u16 bmsr, u16 lpa, u16 status, struct phylink_link_state *state); int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port); unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port); int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port); int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip, int port, uint8_t *data); size_t mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port, uint64_t *data); int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port); int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip, int port, uint8_t *data); size_t mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port, uint64_t *data); int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port); void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p); int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port); void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p); int mv88e6352_serdes_set_tx_amplitude(struct mv88e6xxx_chip *chip, int port, int val); /* Return the (first) SERDES lane address a port is using, -errno otherwise. */ static inline int mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) { … } static inline unsigned int mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port) { … } extern const struct mv88e6xxx_pcs_ops mv88e6185_pcs_ops; extern const struct mv88e6xxx_pcs_ops mv88e6352_pcs_ops; extern const struct mv88e6xxx_pcs_ops mv88e6390_pcs_ops; extern const struct mv88e6xxx_pcs_ops mv88e6393x_pcs_ops; #endif
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