// SPDX-License-Identifier: GPL-2.0-or-later /* * Marvell 88E6xxx Switch Port Registers support * * Copyright (c) 2008 Marvell Semiconductor * * Copyright (c) 2016-2017 Savoir-faire Linux Inc. * Vivien Didelot <[email protected]> */ #include <linux/bitfield.h> #include <linux/if_bridge.h> #include <linux/phy.h> #include <linux/phylink.h> #include "chip.h" #include "global2.h" #include "port.h" #include "serdes.h" int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, u16 *val) { … } int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, int bit, int val) { … } int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, u16 val) { … } /* Offset 0x00: MAC (or PCS or Physical) Status Register * * For most devices, this is read only. However the 6185 has the MyPause * bit read/write. */ int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, int pause) { … } /* Offset 0x01: MAC (or PCS or Physical) Control Register * * Link, Duplex and Flow Control have one force bit, one value bit. * * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value. * Alternative values require the 200BASE (or AltSpeed) bit 12 set. * Newer chips need a ForcedSpd bit 13 set to consider the value. */ static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode) { … } int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode) { … } int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode) { … } int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode) { … } int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) { … } int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) { … } int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) { … } static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, bool alt_bit, bool force_bit, int duplex) { … } /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */ int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex) { … } /* Support 10, 100 Mbps (e.g. 88E6250 family) */ int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex) { … } /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */ int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex) { … } phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip, int port) { … } /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */ int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex) { … } /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */ int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex) { … } phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip, int port) { … } /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */ int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex) { … } phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip, int port) { … } /* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X) * Function mv88e6xxx_port_set_speed_duplex() can't be used as the register * values for speeds 2500 & 5000 conflict. */ int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex) { … } phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip, int port) { … } static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode, bool force) { … } int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode) { … } int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode) { … } int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode) { … } static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip, int port) { … } int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode) { … } int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) { … } int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) { … } /* Offset 0x02: Jamming Control * * Do not limit the period of time that this port can be paused for by * the remote end or the period of time that this port can pause the * remote end. */ int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, u8 out) { … } int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, u8 out) { … } /* Offset 0x04: Port Control Register */ static const char * const mv88e6xxx_port_state_names[] = …; int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) { … } int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, enum mv88e6xxx_egress_mode mode) { … } int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, enum mv88e6xxx_frame_mode mode) { … } int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, enum mv88e6xxx_frame_mode mode) { … } int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, int port, bool unicast) { … } int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, bool unicast) { … } int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, bool multicast) { … } /* Offset 0x05: Port Control 1 */ int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, bool message_port) { … } int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, bool trunk, u8 id) { … } /* Offset 0x06: Port Based VLAN Map */ int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) { … } int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) { … } int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) { … } /* Offset 0x07: Default Port VLAN ID & Priority */ int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) { … } int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) { … } /* Offset 0x08: Port Control 2 Register */ static const char * const mv88e6xxx_port_8021q_mode_names[] = …; int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, int port, bool multicast) { … } int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, int upstream_port) { … } int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, enum mv88e6xxx_egress_direction direction, bool mirror) { … } int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, bool locked) { … } int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, u16 mode) { … } int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, bool drop_untagged) { … } int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map) { … } int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, size_t size) { … } /* Offset 0x09: Port Rate Control */ int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) { … } int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) { … } /* Offset 0x0B: Port Association Vector */ int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, u16 pav) { … } /* Offset 0x0C: Port ATU Control */ int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) { … } /* Offset 0x0D: (Priority) Override Register */ int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) { … } /* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */ static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port, u16 pointer, u8 *data) { … } static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port, u16 pointer, u8 data) { … } static int mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip *chip, u16 pointer, u8 data) { … } int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, enum mv88e6xxx_egress_direction direction, int port) { … } int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, int upstream_port) { … } int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) { … } /* Offset 0x10 & 0x11: EPC */ static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port) { … } /* Port Ether type for 6393X family */ int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, u16 etype) { … } /* Offset 0x0f: Port Ether type */ int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, u16 etype) { … } /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3] * Offset 0x19: Port IEEE Priority Remapping Registers [4-7] */ int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) { … } static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, int port, u16 table, u8 ptr, u16 data) { … } int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) { … } /* Offset 0x0E: Policy Control Register */ static int mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping, enum mv88e6xxx_policy_action action, u16 *mask, u16 *val, int *shift) { … } int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, enum mv88e6xxx_policy_mapping mapping, enum mv88e6xxx_policy_action action) { … } int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, enum mv88e6xxx_policy_mapping mapping, enum mv88e6xxx_policy_action action) { … }
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