/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Microsemi Ocelot Switch driver * * Copyright (c) 2017 Microsemi Corporation */ #ifndef _MSCC_OCELOT_DEV_H_ #define _MSCC_OCELOT_DEV_H_ #define DEV_CLOCK_CFG_MAC_TX_RST … #define DEV_CLOCK_CFG_MAC_RX_RST … #define DEV_CLOCK_CFG_PCS_TX_RST … #define DEV_CLOCK_CFG_PCS_RX_RST … #define DEV_CLOCK_CFG_PORT_RST … #define DEV_CLOCK_CFG_PHY_RST … #define DEV_CLOCK_CFG_LINK_SPEED(x) … #define DEV_CLOCK_CFG_LINK_SPEED_M … #define DEV_PORT_MISC_FWD_ERROR_ENA … #define DEV_PORT_MISC_FWD_PAUSE_ENA … #define DEV_PORT_MISC_FWD_CTRL_ENA … #define DEV_PORT_MISC_DEV_LOOP_ENA … #define DEV_PORT_MISC_HDX_FAST_DIS … #define DEV_EEE_CFG_EEE_ENA … #define DEV_EEE_CFG_EEE_TIMER_AGE(x) … #define DEV_EEE_CFG_EEE_TIMER_AGE_M … #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) … #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) … #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M … #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) … #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) … #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M … #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) … #define DEV_EEE_CFG_PORT_LPI … #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) … #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M … #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x) … #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x) … #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M … #define DEV_MAC_ENA_CFG_RX_ENA … #define DEV_MAC_ENA_CFG_TX_ENA … #define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA … #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA … #define DEV_MAC_MODE_CFG_FDX_ENA … #define DEV_MAC_TAGS_CFG_TAG_ID(x) … #define DEV_MAC_TAGS_CFG_TAG_ID_M … #define DEV_MAC_TAGS_CFG_TAG_ID_X(x) … #define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA … #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA … #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA … #define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA … #define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK … #define DEV_MAC_IFG_CFG_REDUCED_TX_IFG … #define DEV_MAC_IFG_CFG_TX_IFG(x) … #define DEV_MAC_IFG_CFG_TX_IFG_M … #define DEV_MAC_IFG_CFG_TX_IFG_X(x) … #define DEV_MAC_IFG_CFG_RX_IFG2(x) … #define DEV_MAC_IFG_CFG_RX_IFG2_M … #define DEV_MAC_IFG_CFG_RX_IFG2_X(x) … #define DEV_MAC_IFG_CFG_RX_IFG1(x) … #define DEV_MAC_IFG_CFG_RX_IFG1_M … #define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC … #define DEV_MAC_HDX_CFG_OB_ENA … #define DEV_MAC_HDX_CFG_WEXC_DIS … #define DEV_MAC_HDX_CFG_SEED(x) … #define DEV_MAC_HDX_CFG_SEED_M … #define DEV_MAC_HDX_CFG_SEED_X(x) … #define DEV_MAC_HDX_CFG_SEED_LOAD … #define DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA … #define DEV_MAC_HDX_CFG_LATE_COL_POS(x) … #define DEV_MAC_HDX_CFG_LATE_COL_POS_M … #define DEV_MAC_DBG_CFG_TBI_MODE … #define DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA … #define DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY … #define DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY … #define DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY … #define DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY … #define DEV_MAC_STICKY_RX_JUNK_STICKY … #define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY … #define DEV_MAC_STICKY_TX_JAM_STICKY … #define DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY … #define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY … #define DEV_MAC_STICKY_TX_ABORT_STICKY … #define DEV_MM_CONFIG_ENABLE_CONFIG_MM_RX_ENA … #define DEV_MM_CONFIG_ENABLE_CONFIG_MM_TX_ENA … #define DEV_MM_CONFIG_ENABLE_CONFIG_KEEP_S_AFTER_D … #define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_DIS … #define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME(x) … #define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_M … #define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_X(x) … #define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS(x) … #define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_M … #define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_X(x) … #define DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STATUS … #define DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STICKY … #define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE(x) … #define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_M … #define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_X(x) … #define DEV_MM_STAT_MM_STATUS_UNEXP_RX_PFRM_STICKY … #define DEV_MM_STAT_MM_STATUS_UNEXP_TX_PFRM_STICKY … #define DEV_MM_STAT_MM_STATUS_MM_RX_FRAME_STATUS … #define DEV_MM_STAT_MM_STATUS_MM_TX_FRAME_STATUS … #define DEV_MM_STAT_MM_STATUS_MM_TX_PRMPT_STATUS … #define PCS1G_CFG_LINK_STATUS_TYPE … #define PCS1G_CFG_AN_LINK_CTRL_ENA … #define PCS1G_CFG_PCS_ENA … #define PCS1G_MODE_CFG_UNIDIR_MODE_ENA … #define PCS1G_MODE_CFG_SGMII_MODE_ENA … #define PCS1G_SD_CFG_SD_SEL … #define PCS1G_SD_CFG_SD_POL … #define PCS1G_SD_CFG_SD_ENA … #define PCS1G_ANEG_CFG_ADV_ABILITY(x) … #define PCS1G_ANEG_CFG_ADV_ABILITY_M … #define PCS1G_ANEG_CFG_ADV_ABILITY_X(x) … #define PCS1G_ANEG_CFG_SW_RESOLVE_ENA … #define PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT … #define PCS1G_ANEG_CFG_ANEG_ENA … #define PCS1G_ANEG_NP_CFG_NP_TX(x) … #define PCS1G_ANEG_NP_CFG_NP_TX_M … #define PCS1G_ANEG_NP_CFG_NP_TX_X(x) … #define PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT … #define PCS1G_LB_CFG_RA_ENA … #define PCS1G_LB_CFG_GMII_PHY_LB_ENA … #define PCS1G_LB_CFG_TBI_HOST_LB_ENA … #define PCS1G_DBG_CFG_UDLT … #define PCS1G_CDET_CFG_CDET_ENA … #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x) … #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M … #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x) … #define PCS1G_ANEG_STATUS_PR … #define PCS1G_ANEG_STATUS_PAGE_RX_STICKY … #define PCS1G_ANEG_STATUS_ANEG_COMPLETE … #define PCS1G_LINK_STATUS_DELAY_VAR(x) … #define PCS1G_LINK_STATUS_DELAY_VAR_M … #define PCS1G_LINK_STATUS_DELAY_VAR_X(x) … #define PCS1G_LINK_STATUS_SIGNAL_DETECT … #define PCS1G_LINK_STATUS_LINK_STATUS … #define PCS1G_LINK_STATUS_SYNC_STATUS … #define PCS1G_STICKY_LINK_DOWN_STICKY … #define PCS1G_STICKY_OUT_OF_SYNC_STICKY … #define PCS1G_LPI_CFG_QSGMII_MS_SEL … #define PCS1G_LPI_CFG_RX_LPI_OUT_DIS … #define PCS1G_LPI_CFG_LPI_TESTMODE … #define PCS1G_LPI_CFG_LPI_RX_WTIM(x) … #define PCS1G_LPI_CFG_LPI_RX_WTIM_M … #define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x) … #define PCS1G_LPI_CFG_TX_ASSERT_LPIDLE … #define PCS1G_LPI_STATUS_RX_LPI_FAIL … #define PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY … #define PCS1G_LPI_STATUS_RX_QUIET … #define PCS1G_LPI_STATUS_RX_LPI_MODE … #define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY … #define PCS1G_LPI_STATUS_TX_QUIET … #define PCS1G_LPI_STATUS_TX_LPI_MODE … #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x) … #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M … #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x) … #define PCS1G_TSTPAT_STATUS_JTP_ERR … #define PCS1G_TSTPAT_STATUS_JTP_LOCK … #define DEV_PCS_FX100_CFG_SD_SEL … #define DEV_PCS_FX100_CFG_SD_POL … #define DEV_PCS_FX100_CFG_SD_ENA … #define DEV_PCS_FX100_CFG_LOOPBACK_ENA … #define DEV_PCS_FX100_CFG_SWAP_MII_ENA … #define DEV_PCS_FX100_CFG_RXBITSEL(x) … #define DEV_PCS_FX100_CFG_RXBITSEL_M … #define DEV_PCS_FX100_CFG_RXBITSEL_X(x) … #define DEV_PCS_FX100_CFG_SIGDET_CFG(x) … #define DEV_PCS_FX100_CFG_SIGDET_CFG_M … #define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x) … #define DEV_PCS_FX100_CFG_LINKHYST_TM_ENA … #define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x) … #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M … #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x) … #define DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA … #define DEV_PCS_FX100_CFG_FEFCHK_ENA … #define DEV_PCS_FX100_CFG_FEFGEN_ENA … #define DEV_PCS_FX100_CFG_PCS_ENA … #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x) … #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M … #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x) … #define DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY … #define DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY … #define DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY … #define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY … #define DEV_PCS_FX100_STATUS_FEF_STATUS … #define DEV_PCS_FX100_STATUS_SIGNAL_DETECT … #define DEV_PCS_FX100_STATUS_SYNC_STATUS … #endif
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