linux/drivers/net/dsa/sja1105/sja1105_mdio.c

// SPDX-License-Identifier: GPL-2.0
/* Copyright 2021 NXP
 */
#include <linux/pcs/pcs-xpcs.h>
#include <linux/of_mdio.h>
#include "sja1105.h"

#define SJA1110_PCS_BANK_REG

int sja1105_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg)
{}

int sja1105_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd,
			       int reg, u16 val)
{}

int sja1110_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg)
{}

int sja1110_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, int reg,
			       u16 val)
{}

enum sja1105_mdio_opcode {};

static u64 sja1105_base_t1_encode_addr(struct sja1105_private *priv,
				       int phy, enum sja1105_mdio_opcode op,
				       int xad)
{}

static int sja1105_base_t1_mdio_read_c22(struct mii_bus *bus, int phy, int reg)
{}

static int sja1105_base_t1_mdio_read_c45(struct mii_bus *bus, int phy,
					 int mmd, int reg)
{}

static int sja1105_base_t1_mdio_write_c22(struct mii_bus *bus, int phy, int reg,
					  u16 val)
{}

static int sja1105_base_t1_mdio_write_c45(struct mii_bus *bus, int phy,
					  int mmd, int reg, u16 val)
{}

static int sja1105_base_tx_mdio_read(struct mii_bus *bus, int phy, int reg)
{}

static int sja1105_base_tx_mdio_write(struct mii_bus *bus, int phy, int reg,
				      u16 val)
{}

static int sja1105_mdiobus_base_tx_register(struct sja1105_private *priv,
					    struct device_node *mdio_node)
{}

static void sja1105_mdiobus_base_tx_unregister(struct sja1105_private *priv)
{}

static int sja1105_mdiobus_base_t1_register(struct sja1105_private *priv,
					    struct device_node *mdio_node)
{}

static void sja1105_mdiobus_base_t1_unregister(struct sja1105_private *priv)
{}

static int sja1105_mdiobus_pcs_register(struct sja1105_private *priv)
{}

static void sja1105_mdiobus_pcs_unregister(struct sja1105_private *priv)
{}

int sja1105_mdiobus_register(struct dsa_switch *ds)
{}

void sja1105_mdiobus_unregister(struct dsa_switch *ds)
{}