/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH * Copyright (c) 2018-2019, Vladimir Oltean <[email protected]> */ #ifndef _SJA1105_H #define _SJA1105_H #include <linux/ptp_clock_kernel.h> #include <linux/timecounter.h> #include <linux/dsa/sja1105.h> #include <linux/dsa/8021q.h> #include <net/dsa.h> #include <linux/mutex.h> #include "sja1105_static_config.h" #define SJA1105ET_FDB_BIN_SIZE … /* The hardware value is in multiples of 10 ms. * The passed parameter is in multiples of 1 ms. */ #define SJA1105_AGEING_TIME_MS(ms) … #define SJA1105_NUM_L2_POLICERS … /* Calculated assuming 1Gbps, where the clock has 125 MHz (8 ns period) * To avoid floating point operations, we'll multiply the degrees by 10 * to get a "phase" and get 1 decimal point precision. */ #define SJA1105_RGMII_DELAY_PS_TO_PHASE(ps) … #define SJA1105_RGMII_DELAY_PHASE_TO_PS(phase) … #define SJA1105_RGMII_DELAY_PHASE_TO_HW(phase) … #define SJA1105_RGMII_DELAY_PS_TO_HW(ps) … /* Valid range in degrees is a value between 73.8 and 101.7 * in 0.9 degree increments */ #define SJA1105_RGMII_DELAY_MIN_PS … #define SJA1105_RGMII_DELAY_MAX_PS … sja1105_spi_rw_mode_t; #include "sja1105_tas.h" #include "sja1105_ptp.h" enum sja1105_stats_area { … }; /* Keeps the different addresses between E/T and P/Q/R/S */ struct sja1105_regs { … }; struct sja1105_mdio_private { … }; enum { … }; enum sja1105_internal_phy_t { … }; struct sja1105_info { … }; enum sja1105_key_type { … }; struct sja1105_key { … }; enum sja1105_rule_type { … }; enum sja1105_vl_type { … }; struct sja1105_rule { … }; struct sja1105_flow_block { … }; struct sja1105_private { … }; #include "sja1105_dynamic_config.h" struct sja1105_spi_message { … }; /* From sja1105_main.c */ enum sja1105_reset_reason { … }; int sja1105_static_config_reload(struct sja1105_private *priv, enum sja1105_reset_reason reason); int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, struct netlink_ext_ack *extack); void sja1105_frame_memory_partitioning(struct sja1105_private *priv); /* From sja1105_mdio.c */ int sja1105_mdiobus_register(struct dsa_switch *ds); void sja1105_mdiobus_unregister(struct dsa_switch *ds); int sja1105_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg); int sja1105_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, int reg, u16 val); int sja1110_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg); int sja1110_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, int reg, u16 val); /* From sja1105_devlink.c */ int sja1105_devlink_setup(struct dsa_switch *ds); void sja1105_devlink_teardown(struct dsa_switch *ds); int sja1105_devlink_info_get(struct dsa_switch *ds, struct devlink_info_req *req, struct netlink_ext_ack *extack); /* From sja1105_spi.c */ int sja1105_xfer_buf(const struct sja1105_private *priv, sja1105_spi_rw_mode_t rw, u64 reg_addr, u8 *buf, size_t len); int sja1105_xfer_u32(const struct sja1105_private *priv, sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value, struct ptp_system_timestamp *ptp_sts); int sja1105_xfer_u64(const struct sja1105_private *priv, sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value, struct ptp_system_timestamp *ptp_sts); int static_config_buf_prepare_for_upload(struct sja1105_private *priv, void *config_buf, int buf_len); int sja1105_static_config_upload(struct sja1105_private *priv); int sja1105_inhibit_tx(const struct sja1105_private *priv, unsigned long port_bitmap, bool tx_inhibited); extern const struct sja1105_info sja1105e_info; extern const struct sja1105_info sja1105t_info; extern const struct sja1105_info sja1105p_info; extern const struct sja1105_info sja1105q_info; extern const struct sja1105_info sja1105r_info; extern const struct sja1105_info sja1105s_info; extern const struct sja1105_info sja1110a_info; extern const struct sja1105_info sja1110b_info; extern const struct sja1105_info sja1110c_info; extern const struct sja1105_info sja1110d_info; /* From sja1105_clocking.c */ sja1105_mii_role_t; sja1105_phy_interface_t; int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port); int sja1110_setup_rgmii_delay(const void *ctx, int port); int sja1105_clocking_setup_port(struct sja1105_private *priv, int port); int sja1105_clocking_setup(struct sja1105_private *priv); int sja1110_disable_microcontroller(struct sja1105_private *priv); /* From sja1105_ethtool.c */ void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data); void sja1105_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data); int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset); /* From sja1105_dynamic_config.c */ int sja1105_dynamic_config_read(struct sja1105_private *priv, enum sja1105_blk_idx blk_idx, int index, void *entry); int sja1105_dynamic_config_write(struct sja1105_private *priv, enum sja1105_blk_idx blk_idx, int index, void *entry, bool keep); enum sja1105_iotag { … }; enum sja1110_vlan_type { … }; enum sja1110_shaper_type { … }; u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid); int sja1105et_fdb_add(struct dsa_switch *ds, int port, const unsigned char *addr, u16 vid); int sja1105et_fdb_del(struct dsa_switch *ds, int port, const unsigned char *addr, u16 vid); int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port, const unsigned char *addr, u16 vid); int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port, const unsigned char *addr, u16 vid); /* From sja1105_flower.c */ int sja1105_cls_flower_del(struct dsa_switch *ds, int port, struct flow_cls_offload *cls, bool ingress); int sja1105_cls_flower_add(struct dsa_switch *ds, int port, struct flow_cls_offload *cls, bool ingress); int sja1105_cls_flower_stats(struct dsa_switch *ds, int port, struct flow_cls_offload *cls, bool ingress); void sja1105_flower_setup(struct dsa_switch *ds); void sja1105_flower_teardown(struct dsa_switch *ds); struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv, unsigned long cookie); #endif
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