linux/drivers/net/dsa/sja1105/sja1105_clocking.c

// SPDX-License-Identifier: BSD-3-Clause
/* Copyright 2016-2018 NXP
 * Copyright (c) 2018-2019, Vladimir Oltean <[email protected]>
 */
#include <linux/packing.h>
#include "sja1105.h"

#define SJA1105_SIZE_CGU_CMD …
#define SJA1110_BASE_MCSS_CLK …
#define SJA1110_BASE_TIMER_CLK …

/* Common structure for CFG_PAD_MIIx_RX and CFG_PAD_MIIx_TX */
struct sja1105_cfg_pad_mii { … };

struct sja1105_cfg_pad_mii_id { … };

/* UM10944 Table 82.
 * IDIV_0_C to IDIV_4_C control registers
 * (addr. 10000Bh to 10000Fh)
 */
struct sja1105_cgu_idiv { … };

/* PLL_1_C control register
 *
 * SJA1105 E/T: UM10944 Table 81 (address 10000Ah)
 * SJA1105 P/Q/R/S: UM11040 Table 116 (address 10000Ah)
 */
struct sja1105_cgu_pll_ctrl { … };

struct sja1110_cgu_outclk { … };

enum { … };

/* UM10944 Table 83.
 * MIIx clock control registers 1 to 30
 * (addresses 100013h to 100035h)
 */
struct sja1105_cgu_mii_ctrl { … };

static void sja1105_cgu_idiv_packing(void *buf, struct sja1105_cgu_idiv *idiv,
				     enum packing_op op)
{ … }

static int sja1105_cgu_idiv_config(struct sja1105_private *priv, int port,
				   bool enabled, int factor)
{ … }

static void
sja1105_cgu_mii_control_packing(void *buf, struct sja1105_cgu_mii_ctrl *cmd,
				enum packing_op op)
{ … }

static int sja1105_cgu_mii_tx_clk_config(struct sja1105_private *priv,
					 int port, sja1105_mii_role_t role)
{ … }

static int
sja1105_cgu_mii_rx_clk_config(struct sja1105_private *priv, int port)
{ … }

static int
sja1105_cgu_mii_ext_tx_clk_config(struct sja1105_private *priv, int port)
{ … }

static int
sja1105_cgu_mii_ext_rx_clk_config(struct sja1105_private *priv, int port)
{ … }

static int sja1105_mii_clocking_setup(struct sja1105_private *priv, int port,
				      sja1105_mii_role_t role)
{ … }

static void
sja1105_cgu_pll_control_packing(void *buf, struct sja1105_cgu_pll_ctrl *cmd,
				enum packing_op op)
{ … }

static int sja1105_cgu_rgmii_tx_clk_config(struct sja1105_private *priv,
					   int port, u64 speed)
{ … }

/* AGU */
static void
sja1105_cfg_pad_mii_packing(void *buf, struct sja1105_cfg_pad_mii *cmd,
			    enum packing_op op)
{ … }

static int sja1105_rgmii_cfg_pad_tx_config(struct sja1105_private *priv,
					   int port)
{ … }

static int sja1105_cfg_pad_rx_config(struct sja1105_private *priv, int port)
{ … }

static void
sja1105_cfg_pad_mii_id_packing(void *buf, struct sja1105_cfg_pad_mii_id *cmd,
			       enum packing_op op)
{ … }

static void
sja1110_cfg_pad_mii_id_packing(void *buf, struct sja1105_cfg_pad_mii_id *cmd,
			       enum packing_op op)
{ … }

/* The RGMII delay setup procedure is 2-step and gets called upon each
 * .phylink_mac_config. Both are strategic.
 * The reason is that the RX Tunable Delay Line of the SJA1105 MAC has issues
 * with recovering from a frequency change of the link partner's RGMII clock.
 * The easiest way to recover from this is to temporarily power down the TDL,
 * as it will re-lock at the new frequency afterwards.
 */
int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port)
{ … }

int sja1110_setup_rgmii_delay(const void *ctx, int port)
{ … }

static int sja1105_rgmii_clocking_setup(struct sja1105_private *priv, int port,
					sja1105_mii_role_t role)
{ … }

static int sja1105_cgu_rmii_ref_clk_config(struct sja1105_private *priv,
					   int port)
{ … }

static int
sja1105_cgu_rmii_ext_tx_clk_config(struct sja1105_private *priv, int port)
{ … }

static int sja1105_cgu_rmii_pll_config(struct sja1105_private *priv)
{ … }

static int sja1105_rmii_clocking_setup(struct sja1105_private *priv, int port,
				       sja1105_mii_role_t role)
{ … }

int sja1105_clocking_setup_port(struct sja1105_private *priv, int port)
{ … }

int sja1105_clocking_setup(struct sja1105_private *priv)
{ … }

static void
sja1110_cgu_outclk_packing(void *buf, struct sja1110_cgu_outclk *outclk,
			   enum packing_op op)
{ … }

int sja1110_disable_microcontroller(struct sja1105_private *priv)
{ … }