/* typhoon.h: chip info for the 3Com 3CR990 family of controllers */ /* Written 2002-2003 by David Dillow <[email protected]> This software may be used and distributed according to the terms of the GNU General Public License (GPL), incorporated herein by reference. Drivers based on or derived from this code fall under the GPL and must retain the authorship, copyright and license notice. This file is not a complete program and may only be used when the entire operating system is licensed under the GPL. This software is available on a public web site. It may enable cryptographic capabilities of the 3Com hardware, and may be exported from the United States under License Exception "TSU" pursuant to 15 C.F.R. Section 740.13(e). This work was funded by the National Library of Medicine under the Department of Energy project number 0274DD06D1 and NLM project number Y1-LM-2015-01. */ /* All Typhoon ring positions are specificed in bytes, and point to the * first "clean" entry in the ring -- ie the next entry we use for whatever * purpose. */ /* The Typhoon basic ring * ringBase: where this ring lives (our virtual address) * lastWrite: the next entry we'll use */ struct basic_ring { … }; /* The Typhoon transmit ring -- same as a basic ring, plus: * lastRead: where we're at in regard to cleaning up the ring * writeRegister: register to use for writing (different for Hi & Lo rings) */ struct transmit_ring { … }; /* The host<->Typhoon ring index structure * This indicates the current positions in the rings * * All values must be in little endian format for the 3XP * * rxHiCleared: entry we've cleared to in the Hi receive ring * rxLoCleared: entry we've cleared to in the Lo receive ring * rxBuffReady: next entry we'll put a free buffer in * respCleared: entry we've cleared to in the response ring * * txLoCleared: entry the NIC has cleared to in the Lo transmit ring * txHiCleared: entry the NIC has cleared to in the Hi transmit ring * rxLoReady: entry the NIC has filled to in the Lo receive ring * rxBuffCleared: entry the NIC has cleared in the free buffer ring * cmdCleared: entry the NIC has cleared in the command ring * respReady: entry the NIC has filled to in the response ring * rxHiReady: entry the NIC has filled to in the Hi receive ring */ struct typhoon_indexes { … } __packed; /* The host<->Typhoon interface * Our means of communicating where things are * * All values must be in little endian format for the 3XP * * ringIndex: 64 bit bus address of the index structure * txLoAddr: 64 bit bus address of the Lo transmit ring * txLoSize: size (in bytes) of the Lo transmit ring * txHi*: as above for the Hi priority transmit ring * rxLo*: as above for the Lo priority receive ring * rxBuff*: as above for the free buffer ring * cmd*: as above for the command ring * resp*: as above for the response ring * zeroAddr: 64 bit bus address of a zero word (for DMA) * rxHi*: as above for the Hi Priority receive ring * * While there is room for 64 bit addresses, current versions of the 3XP * only do 32 bit addresses, so the *Hi for each of the above will always * be zero. */ struct typhoon_interface { … } __packed; /* The Typhoon transmit/fragment descriptor * * A packet is described by a packet descriptor, followed by option descriptors, * if any, then one or more fragment descriptors. * * Packet descriptor: * flags: Descriptor type * len:i zero, or length of this packet * addr*: 8 bytes of opaque data to the firmware -- for skb pointer * processFlags: Determine offload tasks to perform on this packet. * * Fragment descriptor: * flags: Descriptor type * len:i length of this fragment * addr: low bytes of DMA address for this part of the packet * addrHi: hi bytes of DMA address for this part of the packet * processFlags: must be zero * * TYPHOON_DESC_VALID is not mentioned in their docs, but their Linux * driver uses it. */ struct tx_desc { … } __packed; /* The TCP Segmentation offload option descriptor * * flags: descriptor type * numDesc: must be 1 * mss_flags: bits 0-11 (little endian) are MSS, 12 is first TSO descriptor * 13 is list TSO descriptor, set both if only one TSO * respAddrLo: low bytes of address of the bytesTx field of this descriptor * bytesTx: total number of bytes in this TSO request * status: 0 on completion */ struct tcpopt_desc { … } __packed; /* The IPSEC Offload descriptor * * flags: descriptor type * numDesc: must be 1 * ipsecFlags: bit 0: 0 -- generate IV, 1 -- use supplied IV * sa1, sa2: Security Association IDs for this packet * reserved: set to 0 */ struct ipsec_desc { … } __packed; /* The Typhoon receive descriptor (Updated by NIC) * * flags: Descriptor type, error indication * numDesc: Always zero * frameLen: the size of the packet received * addr: low 32 bytes of the virtual addr passed in for this buffer * addrHi: high 32 bytes of the virtual addr passed in for this buffer * rxStatus: Error if set in flags, otherwise result of offload processing * filterResults: results of filtering on packet, not used * ipsecResults: Results of IPSEC processing * vlanTag: the 801.2q TCI from the packet */ struct rx_desc { … } __packed; /* The Typhoon free buffer descriptor, used to give a buffer to the NIC * * physAddr: low 32 bits of the bus address of the buffer * physAddrHi: high 32 bits of the bus address of the buffer, always zero * virtAddr: low 32 bits of the skb address * virtAddrHi: high 32 bits of the skb address, always zero * * the virt* address is basically two 32 bit cookies, just passed back * from the NIC */ struct rx_free { … } __packed; /* The Typhoon command descriptor, used for commands and responses * * flags: descriptor type * numDesc: number of descriptors following in this command/response, * ie, zero for a one descriptor command * cmd: the command * seqNo: sequence number (unused) * parm1: use varies by command * parm2: use varies by command * parm3: use varies by command */ struct cmd_desc { … } __packed; /* The Typhoon response descriptor, see command descriptor for details */ struct resp_desc { … } __packed; #define INIT_COMMAND_NO_RESPONSE(x, command) … /* We set seqNo to 1 if we're expecting a response from this command */ #define INIT_COMMAND_WITH_RESPONSE(x, command) … /* TYPHOON_CMD_SET_RX_FILTER filter bits (cmd.parm1) */ #define TYPHOON_RX_FILTER_DIRECTED … #define TYPHOON_RX_FILTER_ALL_MCAST … #define TYPHOON_RX_FILTER_BROADCAST … #define TYPHOON_RX_FILTER_PROMISCOUS … #define TYPHOON_RX_FILTER_MCAST_HASH … /* TYPHOON_CMD_READ_STATS response format */ struct stats_resp { … } __packed; /* TYPHOON_CMD_XCVR_SELECT xcvr values (resp.parm1) */ #define TYPHOON_XCVR_10HALF … #define TYPHOON_XCVR_10FULL … #define TYPHOON_XCVR_100HALF … #define TYPHOON_XCVR_100FULL … #define TYPHOON_XCVR_AUTONEG … /* TYPHOON_CMD_READ_MEDIA_STATUS (resp.parm1) */ #define TYPHOON_MEDIA_STAT_CRC_STRIP_DISABLE … #define TYPHOON_MEDIA_STAT_COLLISION_DETECT … #define TYPHOON_MEDIA_STAT_CARRIER_SENSE … #define TYPHOON_MEDIA_STAT_POLARITY_REV … #define TYPHOON_MEDIA_STAT_NO_LINK … /* TYPHOON_CMD_SET_MULTICAST_HASH enable values (cmd.parm1) */ #define TYPHOON_MCAST_HASH_DISABLE … #define TYPHOON_MCAST_HASH_ENABLE … #define TYPHOON_MCAST_HASH_SET … /* TYPHOON_CMD_CREATE_SA descriptor and settings */ struct sa_descriptor { … } __packed; /* TYPHOON_CMD_SET_OFFLOAD_TASKS bits (cmd.parm2 (Tx) & cmd.parm3 (Rx)) * This is all for IPv4. */ #define TYPHOON_OFFLOAD_TCP_CHKSUM … #define TYPHOON_OFFLOAD_UDP_CHKSUM … #define TYPHOON_OFFLOAD_IP_CHKSUM … #define TYPHOON_OFFLOAD_IPSEC … #define TYPHOON_OFFLOAD_BCAST_THROTTLE … #define TYPHOON_OFFLOAD_DHCP_PREVENT … #define TYPHOON_OFFLOAD_VLAN … #define TYPHOON_OFFLOAD_FILTERING … #define TYPHOON_OFFLOAD_TCP_SEGMENT … /* TYPHOON_CMD_ENABLE_WAKE_EVENTS bits (cmd.parm1) */ #define TYPHOON_WAKE_MAGIC_PKT … #define TYPHOON_WAKE_LINK_EVENT … #define TYPHOON_WAKE_ICMP_ECHO … #define TYPHOON_WAKE_ARP … /* These are used to load the firmware image on the NIC */ struct typhoon_file_header { … } __packed; struct typhoon_section_header { … } __packed; /* The Typhoon Register offsets */ #define TYPHOON_REG_SOFT_RESET … #define TYPHOON_REG_INTR_STATUS … #define TYPHOON_REG_INTR_ENABLE … #define TYPHOON_REG_INTR_MASK … #define TYPHOON_REG_SELF_INTERRUPT … #define TYPHOON_REG_HOST2ARM7 … #define TYPHOON_REG_HOST2ARM6 … #define TYPHOON_REG_HOST2ARM5 … #define TYPHOON_REG_HOST2ARM4 … #define TYPHOON_REG_HOST2ARM3 … #define TYPHOON_REG_HOST2ARM2 … #define TYPHOON_REG_HOST2ARM1 … #define TYPHOON_REG_HOST2ARM0 … #define TYPHOON_REG_ARM2HOST3 … #define TYPHOON_REG_ARM2HOST2 … #define TYPHOON_REG_ARM2HOST1 … #define TYPHOON_REG_ARM2HOST0 … #define TYPHOON_REG_BOOT_DATA_LO … #define TYPHOON_REG_BOOT_DATA_HI … #define TYPHOON_REG_BOOT_DEST_ADDR … #define TYPHOON_REG_BOOT_CHECKSUM … #define TYPHOON_REG_BOOT_LENGTH … #define TYPHOON_REG_DOWNLOAD_BOOT_ADDR … #define TYPHOON_REG_DOWNLOAD_HMAC_0 … #define TYPHOON_REG_DOWNLOAD_HMAC_1 … #define TYPHOON_REG_DOWNLOAD_HMAC_2 … #define TYPHOON_REG_DOWNLOAD_HMAC_3 … #define TYPHOON_REG_DOWNLOAD_HMAC_4 … #define TYPHOON_REG_BOOT_RECORD_ADDR_HI … #define TYPHOON_REG_BOOT_RECORD_ADDR_LO … #define TYPHOON_REG_TX_LO_READY … #define TYPHOON_REG_CMD_READY … #define TYPHOON_REG_TX_HI_READY … #define TYPHOON_REG_COMMAND … #define TYPHOON_REG_HEARTBEAT … #define TYPHOON_REG_STATUS … /* 3XP Reset values (TYPHOON_REG_SOFT_RESET) */ #define TYPHOON_RESET_ALL … #define TYPHOON_RESET_NONE … /* 3XP irq bits (TYPHOON_REG_INTR{STATUS,ENABLE,MASK}) * * Some of these came from OpenBSD, as the 3Com docs have it wrong * (INTR_SELF) or don't list it at all (INTR_*_ABORT) * * Enabling irqs on the Heartbeat reg (ArmToHost3) gets you an irq * about every 8ms, so don't do it. */ #define TYPHOON_INTR_HOST_INT … #define TYPHOON_INTR_ARM2HOST0 … #define TYPHOON_INTR_ARM2HOST1 … #define TYPHOON_INTR_ARM2HOST2 … #define TYPHOON_INTR_ARM2HOST3 … #define TYPHOON_INTR_DMA0 … #define TYPHOON_INTR_DMA1 … #define TYPHOON_INTR_DMA2 … #define TYPHOON_INTR_DMA3 … #define TYPHOON_INTR_MASTER_ABORT … #define TYPHOON_INTR_TARGET_ABORT … #define TYPHOON_INTR_SELF … #define TYPHOON_INTR_RESERVED … #define TYPHOON_INTR_BOOTCMD … #define TYPHOON_INTR_ENABLE_ALL … #define TYPHOON_INTR_ALL … #define TYPHOON_INTR_NONE … /* The commands for the 3XP chip (TYPHOON_REG_COMMAND) */ #define TYPHOON_BOOTCMD_BOOT … #define TYPHOON_BOOTCMD_WAKEUP … #define TYPHOON_BOOTCMD_DNLD_COMPLETE … #define TYPHOON_BOOTCMD_SEG_AVAILABLE … #define TYPHOON_BOOTCMD_RUNTIME_IMAGE … #define TYPHOON_BOOTCMD_REG_BOOT_RECORD … /* 3XP Status values (TYPHOON_REG_STATUS) */ #define TYPHOON_STATUS_WAITING_FOR_BOOT … #define TYPHOON_STATUS_SECOND_INIT … #define TYPHOON_STATUS_RUNNING … #define TYPHOON_STATUS_WAITING_FOR_HOST … #define TYPHOON_STATUS_WAITING_FOR_SEGMENT … #define TYPHOON_STATUS_SLEEPING … #define TYPHOON_STATUS_HALTED …
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